Patent US3459966A successfully refreshed from Google Patents.
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US3459966A Expired / Lapsed US ⏱️ 0.0 years remaining

Leakage current elimination

Assignee: RTX Corp
•
Filing: 1964-05-27
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Granted: 1969-08-05
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Expires: 1984-05-27
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Abstract

No abstract record available.

Inventors

  • 👤 Charles B Brahm

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 06:15
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/601; H03K17/06

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 264 words
A SWITCHING CIRCUIT INCLUDING IN COMBINATION A FIRST AND A SECOND TRANSISTOR OF ONE CONDUCTIVELY TYPE, A THIRD AND A FOURTH TRANSISTOR OF THE OPPOSITIVE CONDUCTIVITY TYPE, EACH TRANSISTOR HAVING AN EMITTER AND A COLLECTOR, A FIRST AND A SECOND AND A THIRD AND A FOURTH AND A FIFTH AND A SIXTH UNILATERAL IMPEDANCE EACH HAVING A HIGH BACK RESISTANCE, MEANS CONNECTING THE FOUR TRANSISTORS IN A BRIDGE CIRCUIT HAVING A FIRST AND A SECOND IMPUT TERMINAL AND A FIRST AND A SECOND OUTPUT TERMINAL, THE EMITTERS OF THE FIRST AND SECOND TRANSISTORS BEING CONNECTED TO THE FIRST INPUT TERMINAL, THE EMITTERS OF THE THIRD AND FOURTH TRANSISTORS BEING COUPLED TO THE SECOND INPUT TERMINAL, THE COLLECTORS OF THE THIRD AND FOURTH TRANSISTORS BEING CONNECTED TO THE RESPECTIVE FIRST AND SECOND OUTPUT TERMINALS, THE COLLECTORS OF THE FIRST AND SECOND TRANSISTORS BEING COUPLED THROUGH THE RESPECTIVE FIRST AND SECOND IMPEDANCES TO THE RESPECTIVE FIRST AND SECOND OUTPUT TERMINALS, A LOAD, MEANS CONNECTING THE LOAD BETWEEN THE OUTPUT TERMINALS, A RESISTOR, MEANS CONNECTING THE RESISTOR TO THE SECOND INPUT TERMINAL, A CONSTANT-CURRENT SOURCE, MEANS CONNECTING THE SOURCE TO THE FIRST INPUT TERMINAL, MEANS INCLUDING A TRANSFORMER AND THE THIRD AND FOURTH IMPEDANCES FOR SELECTIVELY RENDERING THE THIRD AND FOURTH TRANSISTORS CONDUCTIVE, MEANS INCLUDING THE FIFTH AND SIXTH IMPEDANCES FOR SELECTIVELY REDERING THE THIRD AND FOURTH TRANSISTORS NONCONDUCTIVE, MEANS SELECTIVELY RENDERING CONDUCTIVE AND NONCONDUCTIVE THE RESPECTIVE FIRST AND SECOND TRANSISTORS IN SYNCHRONISM WITH THE RESPECTIVE FOURTH AND THIRD TRANSISTORS, AND MEANS RESPONSIVE TO THE VOLTAGE ACROSS THE RESISTOR FOR CONTROLLING THE OUTPUT CURRENT OF THE SOURCE.
Claim 2
Dependent Claim 264 words
A SWITCHING CIRCUIT INCLUDING IN COMBINATION A FIRST AND A SECOND TRANSISTOR OF ONE CONDUCTIVELY TYPE, A THIRD AND A FOURTH TRANSISTOR OF THE OPPOSITIVE CONDUCTIVITY TYPE, EACH TRANSISTOR HAVING AN EMITTER AND A COLLECTOR, A FIRST AND A SECOND AND A THIRD AND A FOURTH AND A FIFTH AND A SIXTH UNILATERAL IMPEDANCE EACH HAVING A HIGH BACK RESISTANCE, MEANS CONNECTING THE FOUR TRANSISTORS IN A BRIDGE CIRCUIT HAVING A FIRST AND A SECOND IMPUT TERMINAL AND A FIRST AND A SECOND OUTPUT TERMINAL, THE EMITTERS OF THE FIRST AND SECOND TRANSISTORS BEING CONNECTED TO THE FIRST INPUT TERMINAL, THE EMITTERS OF THE THIRD AND FOURTH TRANSISTORS BEING COUPLED TO THE SECOND INPUT TERMINAL, THE COLLECTORS OF THE THIRD AND FOURTH TRANSISTORS BEING CONNECTED TO THE RESPECTIVE FIRST AND SECOND OUTPUT TERMINALS, THE COLLECTORS OF THE FIRST AND SECOND TRANSISTORS BEING COUPLED THROUGH THE RESPECTIVE FIRST AND SECOND IMPEDANCES TO THE RESPECTIVE FIRST AND SECOND OUTPUT TERMINALS, A LOAD, MEANS CONNECTING THE LOAD BETWEEN THE OUTPUT TERMINALS, A RESISTOR, MEANS CONNECTING THE RESISTOR TO THE SECOND INPUT TERMINAL, A CONSTANT-CURRENT SOURCE, MEANS CONNECTING THE SOURCE TO THE FIRST INPUT TERMINAL, MEANS INCLUDING A TRANSFORMER AND THE THIRD AND FOURTH IMPEDANCES FOR SELECTIVELY RENDERING THE THIRD AND FOURTH TRANSISTORS CONDUCTIVE, MEANS INCLUDING THE FIFTH AND SIXTH IMPEDANCES FOR SELECTIVELY REDERING THE THIRD AND FOURTH TRANSISTORS NONCONDUCTIVE, MEANS SELECTIVELY RENDERING CONDUCTIVE AND NONCONDUCTIVE THE RESPECTIVE FIRST AND SECOND TRANSISTORS IN SYNCHRONISM WITH THE RESPECTIVE FOURTH AND THIRD TRANSISTORS, AND MEANS RESPONSIVE TO THE VOLTAGE ACROSS THE RESISTOR FOR CONTROLLING THE OUTPUT CURRENT OF THE SOURCE.

References Cited (Backward Citations)

US3132303A Cited
US3235751A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1972-08-04 1973-02-03 1973-08-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1976-08-04 1977-02-03 1977-08-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1980-08-04 1981-02-03 1981-08-05 $7700.00 Window Closed / Lapsed

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