Patent US3412240A successfully refreshed from Google Patents.
US3412240A
Expired / Lapsed
US
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Linear interpolater
Assignee: General Precision Systems Inc
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Filing: 1963-02-21
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Granted: 1968-11-19
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Expires: 1983-02-21
Abstract
No abstract record available.
Inventors
- 👤 John M Hunt
- 👤 Kaufmann John
- 👤 Harold R Dell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:04
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/17
Claims Analysis
Total Claims: 1
Claim 1
Independent Claim
328 words
COMPUTING APPARATUS FOR GENERATING OUTPUT SIGNALS CORRESPONDING TO THE VALUE OF A PRE-DETERMINED FUNCTION OF AN INDEPENDENT QUANTITY WHICH IS REPRESENTED BY A PLURALITY OF BINARY CODED INPUT SIGNALS RECEIVED IN PARALLEL, SAID APPARATUS COMPRISING A STORAGE MEANS WHEREIN VALUES OF THE FUNCTION ARE RECORDED CORRESPONDING TO POINTS WHICH ARE SPACED UNIFORMLY WITH RESPECT TO THE INDEPENDENT QUANTITY, AMPLIFIER MEANS FOR REPRODUCING SUCCESSIVE POINT VALUES OF THE FUNCTION FROM THE STORAGE MEANS, EACH FUNCTION POINT VALUE BEING REPRODUCED AS BINARY CODED WORDS WHEREIN BINARY DIGITS ARE REPRODUCED IN PARALLEL, COUNTING MEANS COUPLED TO THE AMPLIFIER MEANS FOR PROVIDING A NUMERICAL COUNT OF THE WORDS REPRODUCED FROM THE STORAGE MEANS, AN INPUT REGISTER FOR RECEIVING AND STORING THE INPUT SIGNALS IN PARALLEL, A COMPARATOR COUPLED TO THE INPUT REGISTER AND TO THE COUNTING MEANS FOR COMPARING THE MOST SIGNIFICANT BINARY DIGITS OF THE INPUT SIGNALS WITH THE NUMERICAL COUNT OF THE REPRODUCED BINARY CODED WORDS, A FIRST MULTIPLICAND REGISTER AND A SECOND MULTIPLICAND REGISTER FOR RECEIVING AND STORING RESPECTIVE BINARY WORDS INPARALLEL, GATING MEANS RESPONSIVELY COUPLED TO THE COMPARATOR AND OPERABLE TO PASS A FIRST SELECTED BINARY CODED WORD FROM THE AMPLIFYING MEANS TO THE FIRST MULTIPLICAND REGISTER AND BEING FURTHER OPERABLE TO PASS THE NEXT SUCCESSIVELY MEANS TO THE BINARY CODED WORD FROM THE AMPLIFYING MEANS TO THE SECOND MULTIPLICAND REGISTER, A MULTIPLIER REGISTER COUPLED TO THE INPUT REGISTER FOR RECEIVING AND STORING THE BINARY DIGITS OF LESSER SIGNIFICANCE OF THE INPUT SIGNALS, A PARALLEL ADDER, AN ACCUMULATOR MEANS COUPLED TO THE ADDER AND OPERABLE TO RECEIVE AND STORE A BINARY CODED SIGNAL IN PARALLEL CONSTITUTING A PARTIAL PRODUCT QUANTITY, GATING MEANS COUPLED BETWEEN THE FIRST MULTIPLICAND REGISTER AND THE ACCUMULATOR FOR INITIALLY ENTERING THE VALUE OF THE FIRST BRACKETING FUNCTION POINT INTO THE ACCUMULATOR, SELECTIVE GATING MEANS RESPONSIVELY COUPLED TO THE MULTIPLIER REGISTER AND OPERABLE TO PASS A QUANTITY FROM A SELECTED ONE OF THE MULTIPLICAND REGISTERS IN ACCORDANCE WITH A VALUE STORED IN THE MULTIPLIER REGISTER.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1971-11-19 | 1972-05-20 | 1972-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1975-11-19 | 1976-05-20 | 1976-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1979-11-19 | 1980-05-20 | 1980-11-19 | $7700.00 | Window Closed / Lapsed |