Simultaneous digital multiply-add, multiply-subtract circuit

Claim 1

A COMPUTER FOR DEVELOPING A QUANTITY WHICH REPRESENTS THE PRODUCT OF A FIRST AND SECOND OPERAND INCREASED OR DECREASED BY A THIRD OPERAND, SAID COMPUTER COMPRISING: A FIRST REGISTER MEANS HAVING N-1 STAGES FOR STORING BINARY SIGNALS REPRESENTING SAID FIRST OPERAND; A PARALLEL ADDED MEANS HAVING N-1 STAGES; PARALLEL CIRCUIT MEANS FOR CONNECTING EACH STAGE OF SAID FIRST REGISTER TO A CORRESPONDING STAGE OF SAID PARALLEL ADDED; A SECOND REGISTER MEANS HAVING N STAGES; PARALLEL CIRCUIT MEANS FOR CONNECTING THE OUTPUT TERMINALS OF EACH BUT THE LEAST SIGNIFICANT STAGE OF SAID SECOND REGISTER TO THE CORRESPONDING STAGES OF SAID PARALLEL ADDER; SWITCHING MEANS HAVING N-1 STAGES, EACH STAGE HAVING A PAIR OF INPUT TERMINALS AND AN OUTPUT TERMINAL; CIRCUIT MEANS FO/R CONNECTING THE PAIR OF INPUT TERMINALS OF EACH STAGE OF SAID SWITCHING MEANS TO THE OUTPUT TERMINALS OF THE STAGES OF SAID PARALLEL ADDER AND ALL BUT THE LEAST SIGNIFICANT STAGE OF SAID SECOND REGISTER RESPECTIVELY; CIRCUIT MEANS FOR CONNECTING THE OUTPUT TERMINALS OF SAID STAGES OF SAID SWITCHING MEANS TO THE INPUT TERMINALS OF ALL BUT THE MOST SIGNIFICANT STAGE OF SAID SECOND REGISTER; MEANS FOR SEQUENTIALLY PROVIDING BINARY SIGNALS REPRESENTING THE DIGITS OF SAID SECOND OPERAND, SAID SWITCHING MEANS BEING RESPONSIVE TO SAID SEQUENTIALLY APPLIED DIGITS OF SAID SECOND OPERAND AND OPERATIVE TO SWITCH ONE OF SAID PAIR OF INPUT TERMINALS TO SAID OUTPUT TERMINALS IN ACCORDANCE WITH THE STAGE OF SAID SEQUENTIALLY APPLIED DIGITS OF SAID SECOND OPERAND; MEANS FOR SEQUENTIALLY PROVIDING BINARY SIGNALS REPRESENTING THE DIGITS OF SAID THIRD OPERAND; AND MEANS FOR SETTING THE MOST SIGNIFICANT STAGE OF SAID SECOND REGISTER IN ACCORDANCE WITH THE SEQUENTIALLY APPLIED DIGITS OF SAID THIRD OPERAND.