Conditional jump sequencing arrangement for a counter register of a computer

Claim 1

A CONDITIONAL JUMP SEQUENCING ARRANGEMENT FOR A TRANSISTORISED COUNTER REGISTER FOR A COMPUTER HAVING N STAGES EACH COMPRISING A TRIGGER CONTROLLED BY A CIRCUIT HAVING TWO INPUTS, WHEN THE SAID INPUTS ARE IN DIFFERENT LOGICAL CONDITIONS, THE TWO INPUTS BEING CONSTITUTED, ONE BY AN AND CIRCUIT SECURING THE CONTENT OF THE TRIGGER UNDER CONSIDERATION AND THE CARRY FROM THE PRECEDING STAGE, THE OTHER BY AN AND CIRCUIT RECEIVING THE COMPLEMENT OF THE TRIGGER IN QUESTION AND THE CARRY FROM THE PRECEDING STAGE, THE ARRANGEMENT BEING CHARACTERIZED BY THE FACT THAT IT COMPRISES FOR A GIVEN STAGE, A FIRST AND CIRCUIT TWO INPUTS OF WHICH RECEIVE, ONE THE CARRY FROM THE PRECEDING STAGE, THE OTHER THE CONTENT OF THE TRIGGER IN QUESTION AND A THIRD INPUT WHICH IS CONSTITUTED BY A COMMAND NOT TO BLOCK THE CARRY SIGNALS, THE FIRST AND CIRCUIT BEING CONNECTED THROUGH A FIRST NOT CIRCUIT TO A SECOND AND CIRCUIT WITH A COMMAND NOT TO PASS THE CARRY SIGNALS, THE OUTPUT OF THIS SECOND ND CIRCUIT BEING CONNECTED TO A SECOND NOT CIRCUIT; THE OUTPUT OF WHICH CONSTITUTES THE CARRY SIGNAL OF THE STAGE IN QUESTION.