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Claim 1

IN AN ELECTRIC BINARY COUNTER AT WHOSE OUTPUTS THERE APPEAR SIGNALS IN NATURAL BINARY CODE AND IN PARALLEL REPRESENTATION, THE COMBINATION WHICH COMPRISES: (A) A SEPARATE ADDER ASSOCIATED WITH EACH BINARY DIGIT, EACH ADDER HAVING A SUM CIRCUIT AND A CARRY CIRCUIT, THE CARRY CIRCUITS OF ALL ADDERS BEING GALVANICALLY COUPLED WITH EACH OTHER; (B) A SEPARATE, CLOCK PULSABLE OUTPUT STORAGE DEVICE ASSOCIATED WITH EACH RESPECTIVE ADDER, EACH STORAGE DEVICE HAVING AN INPUT CONNECTED TO THE SUM CIRCUIT OF ITS RESPECTIVE ADDER AND AN OUTPUT CONNECTED TO FEED THE SUM SIGNAL BACK INTO AN INPUT OF SAID RESPECTIVE ADDER; (C) MEANS FOR CONSTANTLY APPLYING THE VALUE L AS ONE OF THE BINARY SIGNALS APPLIED TO THE ADDER ASSOCIATED WITH THE LOWEST BINARY DIGIT; (D) A SEPARATE, CLOCK PULSABLE INTERMEDIATE STORAGE DEVICE ASSOCIATED WITH EACH BINARY DIGIT, EACH INTERMEDIATE STORAGE DEVICE HAVING AN INPUT CONNECTED TO RECEIVE SAID OUTPUT FROM THE RESPECTIVE OUTPUT STORAGE DEVICE AND AN OUTPUT CONNECTED TO DELIVER THE SUM SIGNAL TO SAID INPUT OF THE RESPECTIVE ADDER; (E) SAID CARRY CIRCUIT OF EACH ADDER BEING SEPARATE FROM SAID SUM CIRCUIT AND BEING CONNECTED AHEAD OF THE RESPECTIVE INTERMEDIATE STORAGE DEVICE, THE LATTER BEING AN AMPLIFIER FOR AMPLIFYING THE CARRY SIGNAL; (F) SAID SUM CIRCUIT OF EACH ADDER BEING CONNECTED AHEAD OF THE RESPECTIVE OUTPUT STORAGE DEVICE, THE LATTER BEING AN AMPLIFIER FOR AMPLIFYING THE SUM SIGNAL; AND (G) SAID CARRY CIRCUIT OF SAID ADDER AND SAID INTERMEDIATE STORAGE DEVICE BEING COMBINED INTO A FIRST MULTIPLE-COMPONENT LOGIC CIRCUIT AND SAID SUM CIRCUIT OF SAID ADDER AND SAID OUTPUT STORAGE DEVICE BEING COMBINED INTO A SECOND MULTIPLE-COMPONENT LOGIC CIRCUIT, SAID FIRST AND SECOND MULTIPLE-COMPONENT LOGIC CIRCUITS BEING SIMILAR TO EACH OTHER.