Controllable timing circuit

Claim 1

ELECTRICAL TIMING WAVE GENERATOR CIRCUIT COMPRISING FOUR TRANSISTORS Q1, Q2, Q3, AND Q4, RESPECTIVELY; MEANS TO BIAS Q1 TO HAVE AN ON STATE IN WHICH ITS COLLECTOR VOLTAGE IS AT A FIRST LEVEL AND AN OFF STATE IN WHICH ITS COLLECTOR VOLTAGE IS AT A SECOND LEVLE NEGATIVE BY A FIXED AMOUNT WITH RESPECT TO SAID FIRST VOLTAGE LEVEL; Q2 HAVING ITS BASE COUPLED TO Q1 COLLECTOR AND ITS COLLECTOR COUPLED TO Q1 BASE; SAID MEANS TO BIAS Q1 BEING ADJUSTED SO THAT WHEN Q2 IS ON Q1 IS ON, AND WHEN Q2 IS OFF Q1 IS OFF; THE BASE OF Q4 BEING COUPLED TO THE COLLECTOR OF Q1; MEANS TO BIAS Q4 SO THAT WHEN Q1 IS ON Q4 IS ON AN WHEN Q1 IS OFF Q4 IS OFF; THE EMITTERS OF Q2 AND Q3 BEING COUPLED TOGETHER TO A COMMON CURRENT SOURCE; MEANS TO BASEBIAS Q2 AND Q3 SO THAT ONLY ONE OF THEM CAN DRAW CURENT FROM SAID SOURCE AT ANY ONE INSTANT OF TIME DEPENDING ON THE RELATIVE MAGNITUDES OF THEIR RESPECTIVE BASE BIASES; THE EMITTER OF Q4 BEING COUPLED TO THE BASE OF Q3 VIA A BIASING CONNECTION CONTAINING RESISTANCE MEANS SUCH THAT Q4 IN THE ON STATE APPLIES TO Q3 BASE A BIAS VOLTAGE AT A THIRD VOLTAGE LEVEL INTERMEDIATE SAID FIRST AND SECOND LEVELS WHEREBY TO HOLD Q3 OFF WHEN Q2 IS ON; AND TIMING INTEGRATOR MEANS INCLUDING CAPACITANCE MEANS CONNECTED TO SAID RESISTANCE MEANS FOR CHARGING SAID CAPACITANCE MEANS THROUGH Q4 WHEN THE LATTER IS ON AND FOR HOLDING Q3 ON FOR A PREDETERMINED PERIOD OF TIME OF DISCHARGE OF SAID CAPACITANCE MEANS THROUGH SAID RESISTANCE MEANS, FOLLOWING AND EVENT WHICH TURNS Q2 OFF; SAID TIMING WAVE BEING THE CURRENT THROUGH Q3 WHEN THE LATTER IS ON FOR SAID PREDETERMINED PERIOD OF TIME.