Divider circuit using delay time to inhibit transistor conduction for predetermined multiple of input pulses

Claim 1

IN A COUNTDOWN CIRCUIT RESPONSIVE TO A NUMBER OF INPUT PULSES COMPRISING A TRANSISTOR, HAVING AT LEAST A COLLECTOR, BASE AND EMITTER JUNCTIONS, A PERIODIC RECURRING INPUT PULSE SIGNAL OF POSITIVE POTENTIAL WITH RESPECT TO GROUND, MEANS CONNECTING SAID SIGNAL DIRECTLY ACROSS THE BASE AND EMITTER JUNCTIONS, MEANS FOR APPLYING A POTENTIAL TO SAID COLLECTOR JUNCTION, SAID POTENTIAL BEING NEGATIVE WITH RESPECT TO SAID INPUT SIGNAL, A DELAY LINE MEANS HAVING A TIME DELAY EQUAL TO A MULTIPLE OF THE PERIOD OF SAID INPUT PULSE, SAID DELAY LINE MEANS CONNECTED BETWEEN SAID COLLECTOR AND BASE JUNCTION SO THAT CERTAIN OF THE PERIODIC INPUT PULSES MAY BE INHIBITED BY BIASING THE TRANSISTOR INTO A NONCONDUCTIVE STATE, IMPEDANCE MEANS CONNECTING THE BASE JUNCTION TO GROUND, MEANS TO ISOLATE THE IMPEDANCE MEANS FROM THE NEGATIVE POTENTIAL MEANS, OUTPUT MEANS CONNECTED TO SAID ISOLATING MEANS AND SAID COLLECTOR JUNCTION, A PERIODIC OUTPUT SIGNAL PRODUCED AT SAID OUTPUT MEANS HAVING PULSES OF A WIDTH EQUAL TO SAID INPUT PULSES.