Complementary symmetry differential pulse integrator

Claim 1

A DIFFERENTIAL PULSE INTEGRATOR COMPRISING A FIRST TRANSISTOR, A SECOND TRANSISTOR OF CONDUCTIVITY TYPE OPPOSITE TO THAT OF SAID FIRST TRANSISTOR, EACH TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, THE COLLECTOR ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS BEING CONNECTED TO EACH OTHER AT A FIRST JUNCTION, MEANS CONNECTED TO THE BASE AND EMITTER ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS TO BIAS SAID FIRST AND SECOND TRANSISTORS TO CUT-OFF, A FIRST SOURCE FOR PRODUCING A FIRST TRAIN OF PULSES, A SECOND SOURCE INDEPENDENT OF SAID FIRST SOURCE FOR PRODUCING A SECOND TRAIN OF PULSES, THE PULSES OF SAID SECOND TRAIN HAVING AREAS INDEPENDENT OF THE AREAS OF THE PULSES OF SAID FIRST TRAIN, SAID SOURCE BEING CONNECTED TO EACH OTHER AT A SECOND JUNCTION, A CAPACITOR FOR APPLYING SAID FIRST TRAIN OF PULSES BETWEEN THE BASE AND EMITTER ELECTRODES OF SAID FIRST TRANSISTOR, A CAPACITOR FOR APPLYING SAID SECOND TRAIN OF PULSES BETWEEN THE BASE AND EMITTER ELECTRODES OF SAID SECOND TRANSISTOR AND A CAPACITOR CONNECTED BETWEEN SAID FIRST AND SECOND JUNCTIONS.