Transistor and method of fabrication to minimize surface recombination effects

Claim 1

A TRANSISTOR COMPRISING: (A) A SEMICONDUCTOR BODY HAVING EMITTER, BASE AND COLLECTOR REGIONS AND HAVING OPPOSED PARALLEL PLANE SURFACES WITH A PERIPHERAL SURFACE THEREBETWEEN; (B) INDIVIDUAL CONNECTIONS TO SAID EMITTER, BASE AND COLLECTOR REGIONS; (C) SAID EMITTER AND BASE REGIONS BEING SEPARATED BY A BARRIER JUNCTION HAVING A PERIPHERAL INTERSECTION WITH ONE OF SAID PLANE SURFACES OF SAID BODY; (D) SAID COLLECTOR REGION EXTENDING INWARDLY OF THE PERIPHERAL SURCACE AND WITHIN THE SEMICONDUCTOR BODY AT A LOCALITY BETWEEN AND SPACED FROM SAID PLANE SURFACES, SAID REGION EXTENDING INWARDLY IN OPPOSITE DIRECTIONS A SUBSTANTIAL DISTANCE BEYOND THE OUTER PERIPHERY OF THE EMITTER REGION AND HAVING A PORTION EXTENDING TO SAID ONE OF SAID PARALLEL PLANE SURFACES; (E) SAID BASE REGION BEING THEREBY CONTOURED TO BE FINE A RELATIVELY SHORT RECTILINEAR PATH LOCATED REMOTELY FROM ANY SURFACE OF SAID BODY FOR CURRENT FLOW BETWEEN SAID BASE CONNECTION AND AN INTERNAL PORTION OF SAID BARRIER JUNCTION REMOTE FROM SAID INTERSECTION AND A RELATIVELY LONG TORTUOUS PATH FOR CURRENT FLOW BETWEEN SAID BASE CONNECTION AND THE PERIPHERAL MARGIN OF SAID BARRIER JUNCTION, WHEREBY THE FLOW OF INJECTED MINORITY CARRIERS ADJACENT THE SURFACE OF THE BODY IS MINIMIZED.