Patent US3278347A successfully refreshed from Google Patents.
US3278347A
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US
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High voltage semiconductor device
Assignee: Infineon Technologies Americas Corp
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Filing: 1963-11-26
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Granted: 1966-10-11
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Expires: 1983-11-26
Abstract
No abstract record available.
Inventors
- 👤 Topas Benjamin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:17
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10D99/00; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/36; H10P50/00; H10P50/69; H10P50/691; H10P50/693; H10P50/694; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
58 words
IN A CONTROLLED RECTIFIER; A WAFER OF SILICON HAVING A FIRST AND SECOND PLANAR JUNCTION THEREIN AND AN EPITAXIALLY GROWN LAYER ON ONE SURFACE PORTION OF SAID WAFER FORMING A THIRD JUNCTION; SAID ONE SURFACE PORTION OF SAID WAFER BEING DEPRESSED BELOW THE SURFACE OF SAID WAFER AND FORMING A CIRCULAR WELL CENTRALLY LOCATED IN SAID WAFER SURFACE.
Claim 2
Dependent Claim
58 words
IN A CONTROLLED RECTIFIER; A WAFER OF SILICON HAVING A FIRST AND SECOND PLANAR JUNCTION THEREIN AND AN EPITAXIALLY GROWN LAYER ON ONE SURFACE PORTION OF SAID WAFER FORMING A THIRD JUNCTION; SAID ONE SURFACE PORTION OF SAID WAFER BEING DEPRESSED BELOW THE SURFACE OF SAID WAFER AND FORMING A CIRCULAR WELL CENTRALLY LOCATED IN SAID WAFER SURFACE.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-10-10 | 1970-04-11 | 1970-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-10-10 | 1974-04-11 | 1974-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-10-10 | 1978-04-11 | 1978-10-11 | $7700.00 | Window Closed / Lapsed |