Logic circuit employing transistor means whereby steady state power dissipation is minimized

Claim 1

THE COMBINATION COMPRISING FIRST AND SECOND TRANSISTOR MEANS OF ONE CONDUCTIVITY TYPE, EACH TRANSISTOR MEANS HAVING AT LEAST ONE CONDUCTION PATH AND TWO CONTROL ELECTRODES; AN OUTPUT TERMINAL, AND FIRST AND SECOND TERMINALS ACROSS WHICH AN OPERATING POTENTIAL MAY BE APPLIED; MEANS CONNECTING THE CONDUCTION PATHS IN CIRCUIT BETWEEN THE OUTPUT TERMINAL AND THE FIRST TERMINAL IN A MANNER PROVIDING FIRST AND SECOND DIFFERENT CIRCUIT PATHS, WHICH INCLUDE THE CONDUCTION PATHS, BETWEEN SAID OUTPUT TERMINAL AND SAID FIRST TERMINAL; FIRST AND SECOND ONES OF SAID CONTROL ELECTRODES BEING LOCATED AT DIFFERENT POINTS ALONG THE LENGTH OF THE FIRST CIRCUIT PATH; THIRD AND FOURTH ONES OF SAID CONTROL ELECTRODES BEING LOCATED AT DIFFERENT POINTS ALONG THE LENGTH OF THE SECOND CIRCUIT PATH; THIRD AND FOURTH TRANSISTOR MEANS OF A SECOND, OPPOSITE CONDUCTIVITY TYPE EACH HAVING AT LEAST ONE CONDUCTION PATH AND TWO CONTROL ELECTRODES; MEANS CONNECTING THE CONDUCTION PATHS OF THE THIRD AND FOURTH TRANSISTOR MEANS IN CIRCUIT BETWEEN THE OUTPUT TERMINAL AND THE SECOND TERMINAL IN A MANNER PROVIDING THIRD AND FOURTH DIFFERENT CIRCUIT PATHS BETWEEN THE OUTPUT TERMINAL AND THE SECOND TERMINAL; FIFTH AND SIXTH CONTROL ELECTRODES BEING LOCATED AT DIFFERENT POINTS ALONG THE LENGTH OF THE THIRD CIRCUIT PATH, AND SEVENTH AND EIGHTH CONTROL ELECTRODES BEING LOCATED AT DIFFERENT POINTS ALONG THE LENGTH OF THE FOURTH CIRCUIT PATH; MEANS FOR APPLYING EACH OF FIRST AND SECOND DIFFERENT INPUT SIGNALS AND SIGNALS REPRESENTING THE COMPLEMENTS OF THE FIRST AND SECOND INPUT SIGNALS TO A DIFFERENT ONE OF THE FIRST, SECOND, THIRD AND FOURTH CONTROL ELECTRODES; AND MEANS FOR APPLYING EACH OF SAID SIGNALS TO A DIFFERENT ONE OF THE FIFTH, SIXTH, SEVENTH AND EIGHTH CONTROL ELECTRODES.