Binary full adder utilizing integrated unipolar transistors

Claim 1

IN COMBINATION, A FIRST TERMINAL TO WHICH AN OPERATING VOLTAGE MAY BE APPLIED AND A SECOND TERMINAL AT A POINT OF REFERENCE POTENTIAL; A FIRST CIRCUIT EXTENDING BETWEEN SAID TERMINALS COMPRISING FIRST, SECOND AND THIRD UNIPOLAR TRANSISTORS CONNECTED IN SERIES SOURCE ELECTRODE TO DRAIN ELECTRODE, EACH SAID TRANSISTOR HAVING A GATE ELECTRODE TO WHICH A CONTROL SIGNAL MAY BE APPLIED, AND SAID SECOND AND THIRD TRANSISTOR RECEIVING THE SAME CONTROL SIGNAL; A SECOND CIRCUIT EXTENDING BETWEEN SAID TERMINALS COMPRISING SAID FIRST UNIPOLAR TRANSISTOR AND FOURTH AND FIFTH UNIPOLAR TRANSISTORS CONNECTED IN SERIES SOURCE ELECTRODE TO DRAIN ELECTRODE, EACH SAID FIRST FORUTH AND FIFTH TRANSISTOR EACH HAVING A GATE ELECTRODE TO WHICH A DIFFERENT CONTROL MAY BE APPLIED; AND A THIRD CIRCUIT EXTENDING BETWEEN SAID TERMINALS COMPRISING SIXTH AND SEVENTH UNIPOLAR TRANSISTORS IN PARALLEL AND SAID THIRD UNIPOLAR TRANSISTOR IN SERIES WITH THE PARALLEL COMBINATION, THE DRAIN ELECTRODE OF SAID THIRD UNIPOLAR TRANSISTOR BEING CONNECTED TO THE COMMON SOURCE ELECTRODE CONNECTION OF SAID PARALLEL CONNECTED TRANSISTORS, SAID SIXTH AND SEVENTH UNIPOLAR TRANSISTORS EACH HAVING A GATE ELECTRODE TO WHICH A DIFFERENT CONTROL SIGNAL MAY BE APPLIED WHEREBY AN OUTPUT SIGNAL APPEARS AT SAID FIRST TERMINAL WHEN SAID FIRST AND SECOND AND THIRD UNIPOLAR TRANSISTORS CONDUCT, OR WHEN FIRST, THIRD AND FOURTH UNIPOLAR TRANSISTOR CONDUCT, OR WHEN SAID FIFTH OR SIXTH AND SEVENTH UNIPOLAR TRANSISTORS CONDUCT.