Anti-race flip-flop

Claim 1

A DIGITAL COMPUTER ONE BIT STORAGE DEVICE ADAPTED TO BE DRIVEN BY FIRST AND SECOND CONCURRENT CLOCK PULSES, EACH OF SAID FIRST AND SECOND CLOCK PULSES BEING OF PREDETERMINED VOLTAGE LEVELS AND AMPLITUDE, SAID ONE BIT STORAGE DEVICE COMPRISING A FIRST BISTABLE STORAGE ELEMENT HAVING FIRST, SECOND, SET AND RESET INPUT TERMINALS FOR PRODUCING FIRST AND SECOND BILEVEL ENERGIZING VOLTAGES; MEANS FOR APPLYING SAID FIRST CLOCK PULSE OF PREDETERMINED VOLTAGE LEVELS TO SAID FIRST INPUT TERMINAL OF SAID FIRST BISTABLE STORAGE ELEMENT THEREBY TO SHIFT THE VOLTAGE LEVELS OF BOTH OF SAID FIRST AND SECOND BILEVEL ENERGIZING VOLTAGES; MEANS CONNECTED TO SAID SET INPUT TERMINAL AND TO SAID RESET INPUT TERMINAL FOR SETTING OR RESETTING SAID FIRST BISTABLE STORAGE ELEMENT THEREBY TO DETERMINE THE STATE THEREOF; GATING MEANS INTERCONNECTED BETWEEN SAID SET AND RESET INPUT TERMINALS AND SAID FIRST AND SECOND INPUT TERMINALS, RESPECTIVELY, OF SAID FIRST BISTABLE STORAGE ELEMENT, SAID GATING MEANS BEING ADAPTED TO RECEIVE SAID SECOND CLOCK PULSE THEREBY TO RESTRICT THE INTERVAL OF TIME DURING WHICH SAID STATE OF SAID FIRST BISTABLE STORAGE ELEMENT CAN BE SET OR RESET TO THE DURATION OF SAID SECOND CLOCK PULSE; AND A SECOND BISTABLE STORAGE ELEMENT HAVING SET AND RESET INPUT TERMINALS ADAPTED TO RECEIVE SAID FIRST AND SECOND BILEVEL ENERGIZING VOLTAGES, RESPECTIVELY, SAID SET AND RESET TERMINALS OF SAID SECOND BISTABLE STORAGE ELEMENT BEING BIASED RELATIVE TO SAID FIRST AND SECOND BILEVEL ENERGIZING VOLTAGES FOR DETERMINING THE STATE THEREOF ONLY DURING NON-SHIFTED PERIODS.