US20050174155A1
Expired / Lapsed
US
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Voltage-controlled analog delay locked loop
Assignee: Promos Technologies Inc
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Filing: 2004-02-11
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Granted: —
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Expires: 2024-02-11
Abstract
Abstract An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch generates three signals that are received by the delay voltage control: a “latched slow signal”, a “latched fast signal”, as well as a “latched fast to slow signal”. The phase detector generates “go fast” and “go slow” signals that are received by the fast/slow latch. The analog delay locked loop sets the initial delay of the delay line at or near its minimum value on start-up. The delay is then forced to increase from the minimum value until a locking condition is achieved independent of the phase relationship between the reference and delayed clock signals.
Inventors
- 👤 John Heightley
- 👤 Steve Eaton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
56 words
1 . An analog delay locked loop comprising: an analog delay line having an associated minimum delay; an input for receiving a reference clock signal; an output for providing a delayed clock signal; and means for controlling the delay through the analog delay line such that the delay is initialized at or near the minimum delay.
Claim 2
Dependent Claim
56 words
1 . An analog delay locked loop comprising: an analog delay line having an associated minimum delay; an input for receiving a reference clock signal; an output for providing a delayed clock signal; and means for controlling the delay through the analog delay line such that the delay is initialized at or near the minimum delay.
Claim 3
Dependent Claim
35 words
2 . The analog delay locked loop according to claim 1 in which the delay through the analog delay line only increases initially, independent of the phase relationship between the reference and delayed clock signals.
Claim 4
Dependent Claim
42 words
3 . The analog delay locked loop according to claim 1 in which the means for controlling the delay through the analog delay line comprises a phase detector for receiving the reference and delayed clock signals and for providing output control signals.
Claim 5
Dependent Claim
33 words
4 . The analog delay locked loop according to claim 3 in which the delay through the analog delay line only increases initially, independent of the output control signals of the phase detector.
Claim 6
Dependent Claim
32 words
5 . The analog delay locked loop according to claim 2 in which the magnitude of incremental delay increases are proportional to the phase difference between the reference and delayed clock signals.
Claim 7
Dependent Claim
48 words
6 . The analog delay locked loop according to claim 3 in which the delay through the analog delay line is increased or decreased after the rising edge of the delayed clock signal is ahead of the rising edge of the reference clock signal by a minimum time.
Claim 8
Dependent Claim
31 words
7 . The analog delay locked loop according to claim 3 in which the phase detector further comprises means for generating a first indication that the delay is to be increased.
Claim 9
Dependent Claim
35 words
8 . The analog delay locked loop according to claim 3 in which the means for controlling the delay through the analog delay line further comprises a fast/slow latch circuit coupled to the phase detector.
Claim 10
Dependent Claim
41 words
9 . The analog delay locked loop according to claim 8 in which the fast/slow latch circuit includes an output for generating a positive going variable width signal for indicating that the delay through the analog delay line should be decreased.
Claim 11
Dependent Claim
41 words
10 . The analog delay locked loop according to claim 8 in which the fast/slow latch circuit includes an output for generating a positive going variable width signal for indicating that the delay through the analog delay line should be increased.
Claim 12
Dependent Claim
41 words
11 . The analog delay locked loop according to claim 8 in which the fast/slow latch circuit includes an output for generating a negative going variable width signal for indicating that the delay through the analog delay line should be increased.
Claim 13
Dependent Claim
46 words
12 . The analog delay locked loop according to claim 8 in which the fast/slow latch circuit includes means for generating first, second, and third output control signals having a width dependent upon the phase difference between the reference clock signal and the delayed clock signal.
Claim 14
Dependent Claim
44 words
13 . The analog delay locked loop according to claim 8 in which the fast/slow latch circuit includes means for generating three variable width signals, two positive signals having a designated minimum high time and one negative signal having a designated minimum low time.
Claim 15
Dependent Claim
69 words
14 . The analog delay locked loop according to claim 8 in which the means for controlling the delay through the analog delay line only responds to a negative going variable width signal generated by the fast/slow latch circuit until a first positive going signal generated by the fast/slow latch for indicating that the delay though the analog delay line should be increased goes positive for a first time.
Claim 16
Dependent Claim
39 words
15 . The analog delay locked loop according to claim 14 in which the fast/slow latch circuit includes means for generating a second positive going signal for indicating that the delay through the analog delay line should be decreased.
Claim 17
Dependent Claim
44 words
16 . The analog delay locked loop according to claim 15 in which, after the first occurrence of the first positive going signal, the means for controlling the delay through the analog delay line only responds to said first and second positive going signals.
Claim 18
Dependent Claim
71 words
17 . The analog delay locked loop according to claim 8 in which the means for controlling the delay through the analog delay line comprises means for generating a first magnitude of control voltage adjusting current until a positive going signal generated by the fast/slow latch for indicating that the delay should be increased goes positive for a first time and, after that, for generating a second magnitude of adjusting current.
Claim 19
Dependent Claim
29 words
18 . The analog delay locked loop according to claim 3 further comprising a reset circuit for preventing a false control signal from being generated by the phase detector.
Claim 20
Dependent Claim
42 words
19 . The analog delay locked loop according to claim 1 further comprising a reset circuit that causes the analog delay locked loop to be reset as soon as the reference clock starts after having been off for a predetermined minimum time.
Claim 21
Dependent Claim
32 words
20 . The analog delay locked loop according to claim 1 in which the means for controlling the delay through the analog delay line further comprises first and second charge integrating capacitors.
Claim 22
Dependent Claim
41 words
21 . The analog delay locked loop according to claim 20 further comprising a reset circuit having a reset time sufficient for the charge integrating capacitors to reset to an initializing value independent of the width of an input reset signal.
Claim 23
Dependent Claim
58 words
22 . The analog delay locked loop according to claim 1 in which the means for controlling the delay through the analog delay line comprises three different levels of DC bias current depending on whether the analog delay locked loop is on with the reference clock signal running, on with the reference clock signal not running, or off.
Claim 24
Dependent Claim
83 words
23 . The analog delay locked loop according to claim 1 in which the means for controlling the delay through the analog delay line comprises: a phase detector having inputs for receiving the reference clock signal and the delayed clock signal; a fast/slow latch having three output control signals coupled to the phase detector; and a delay voltage control circuit having an input coupled to the fast/slow latch and an output coupled to the analog delay line and at least one integrating capacitor.
Claim 25
Dependent Claim
119 words
24 . An analog delay locked loop comprising: a clock input; a sync output; a phase detector coupled to the clock input and sync output; a fast/slow latch for generating three output control signals coupled to the phase detector; a delay voltage control circuit coupled to the fast/slow latch having first and second outputs; first and second integrating capacitors respectively coupled to the first and second outputs of the delay voltage control circuit; a voltage controlled analog delay line having an input coupled to the clock input, first and second control terminals respectively coupled to the first and second outputs of the delay voltage control circuit, and an output coupled to the sync output through a fixed delay line.
Claim 26
Dependent Claim
119 words
24 . An analog delay locked loop comprising: a clock input; a sync output; a phase detector coupled to the clock input and sync output; a fast/slow latch for generating three output control signals coupled to the phase detector; a delay voltage control circuit coupled to the fast/slow latch having first and second outputs; first and second integrating capacitors respectively coupled to the first and second outputs of the delay voltage control circuit; a voltage controlled analog delay line having an input coupled to the clock input, first and second control terminals respectively coupled to the first and second outputs of the delay voltage control circuit, and an output coupled to the sync output through a fixed delay line.
Claim 27
Dependent Claim
79 words
25 . A method for operating an analog delay locked loop including an analog delay line having an associated minimum delay, an input for receiving a reference clock signal, an output for providing a delayed clock signal, the method comprising voltage controlling the delay through the analog delay line such that the delay is initialized at or near the minimum delay and initially only increasing the delay independently of the phase relationship between the reference and delayed clock signals.
Claim 28
Dependent Claim
79 words
25 . A method for operating an analog delay locked loop including an analog delay line having an associated minimum delay, an input for receiving a reference clock signal, an output for providing a delayed clock signal, the method comprising voltage controlling the delay through the analog delay line such that the delay is initialized at or near the minimum delay and initially only increasing the delay independently of the phase relationship between the reference and delayed clock signals.
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