System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line

Claim 2

A circuit comprising: a voltage controlled delay line configured to receive a system clock signal and to output a synchronization clock signal by applying a delay to said system clock signal; and a delay voltage control circuit for supplying a first and a second control voltage to said voltage controlled delay line to control said applying a delay by said voltage controlled delay line, said delay voltage control circuit including a correction magnitude circuit operative to control a level of said first control voltage such that a difference between successive levels in said first control voltage level increases as said first control voltage levels become greater and decreases as said first control voltage levels become lower; wherein the correction magnitude circuit is configured to control the level of the first control voltage and the difference between the successive levels based on a magnitude of current flowing through a correction portion including a control element for controlling the magnitude of the current flowing therethrough and wherein the control element operates in response to a feedback signal comprising the level of the first control voltage to decrease the magnitude of the current flowing as the level of the first control voltage decreases and to increase the magnitude of the current flowing as the level of the first control voltage increases, thereby controlling the difference as a function of the level of the first control voltage.

Claim 3

The circuit of claim 1 wherein said delay voltage control circuit is operative to control said level of said first control voltage such that said difference between successive levels becomes smaller as said first control voltage is reduced from an initial level thereof.

Claim 4

The circuit of claim 2 wherein said delay voltage control circuit is further operative to control said level of said first control voltage such that said difference between successive levels becomes greater as said first control voltage is increased from a lower level thereof toward said initial level thereof.

Claim 5

The circuit of claim 1 further comprising: a phase detector for receiving said system and synchronization clock signals and producing an output signal indicative a phase relationship between said system and synchronization clock signals; a latch circuit coupled to receive said output signal from said phase detector and producing a fast/slow signal for input to said delay voltage control circuit, said voltage controlled delay line providing said synchronization clock signal for input to said phase detector.

Claim 6

The circuit of claim 4 further comprising: a fixed delay line circuit coupled to said voltage controlled delay line for providing said synchronization clock signal for input to said phase detector.

Claim 7

The circuit of claim 4 wherein said phase detector, said latch circuit, said delay voltage control circuit and said voltage controlled delay line comprise a delay locked loop circuit.

Claim 8

The circuit of claim 6 wherein said delay locked loop circuit is integrated with a DDR DRAM.

Claim 9

The circuit of claim 1 , wherein the second control voltage is generated by the delay voltage control circuit from the first control voltage such that a level of said second control voltage decreases and increases inversely to said level of said first control voltage.

Claim 10

The circuit of claim 1 , wherein the first control voltage controls N-channel devices in said voltage controlled delay line and the second control voltage controls P-channel devices in said voltage controlled delay line.

Claim 11

The circuit of claim 1 , wherein the level of the first control voltage is decreased by the correction magnitude circuit in response to a decrease in the magnitude of the current flowing in the correction portion.

Claim 14

A circuit for compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line, said circuit comprising: means for providing at least one control voltage at a level thereof to said voltage controlled delay line; means for implementing a series of changes in said control voltage level; and means for controlling said series of changes in said control voltage level such that a difference between successive ones of said control voltage levels increases as said control voltage levels become greater and decreases as said control voltage levels become lower.

Claim 15

A circuit for compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line, said circuit comprising: means for providing at least one control voltage at a level thereof to said voltage controlled delay line; means for implementing a series of changes in said control voltage level; and means for controlling said series of changes in said control voltage level such that a difference between successive ones of said control voltage levels increases as said control voltage levels become greater and decreases as said control voltage levels become lower.

Claim 16

The circuit of claim 12 wherein said means for controlling said series of changes in said control voltage level comprises: means for making said difference between successive ones of said control voltage levels a function of said control voltage.

Claim 17

The circuit of claim 13 wherein said means for controlling said series of changes in said control voltage level comprises: means for controlling said series of changes in said control voltage level such that the difference between successive ones of said control voltage levels becomes smaller as said control voltage is reduced from an initial level.

Claim 18

The circuit of claim 14 wherein said means for controlling said series of changes in said control voltage level comprises: means for controlling said series of changes in said control voltage level such that the difference between successive ones of said control voltage levels becomes greater as said control voltage is increased from a lower level thereof toward said initial level.

Claim 19

The circuit of claim 13 wherein said means for controlling said series of changes in said control voltage level comprises: means for controlling said series of changes in said control voltage level such that the difference between successive ones of said control voltage levels becomes smaller as said control voltage is decreased from an initial level.

Claim 20

The circuit of claim 16 wherein said means for controlling said series of changes in said control voltage level comprises: means for controlling said series of changes in said control voltage level such that the difference between successive ones of said control voltage levels becomes greater as said control voltage is decreased from a higher level thereof toward said initial level.

Claim 21

A circuit for compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line, said circuit receiving at least one fast/slow input signal comprising: a delay voltage control circuit for receiving said at least one fast/slow input signal and producing at least one control voltage to said voltage controlled delay line in response thereto, said delay voltage control circuit operative to control a level of said at least one control voltage such that a difference between successive levels in said control voltage level increases as said control voltage levels become greater and decreases as said control voltage levels become lower, wherein said at least one fast/slow input signal comprises separate “fast” and “slow” input signals and wherein said delay voltage control circuit comprises: first, second, third and fourth series coupled switching devices having a first circuit node thereof and coupled between a supply voltage line and a reference voltage line, each of said series coupled switching devices including a control terminal thereof, said separate “fast” and “slow” input signals being respectively coupled to said control terminal of said first and fourth switching devices and said control terminal of said third switching device being coupled to said first circuit node intermediate said second and third switching devices to provide said at least one control voltage; and fifth and sixth series coupled switching devices having a second circuit node therebetween and coupled between said supply voltage line and said reference voltage line, each of said fifth and sixth switching devices including a control terminal thereof, said control terminal of said sixth switching device being coupled to said first circuit node to provide a first control voltage and said control terminal of said fifth switching device being coupled to said control terminal of said second switching device and to said second circuit node to provide a second control voltage.

Claim 22

A circuit for compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line, said circuit receiving at least one fast/slow input signal comprising: a delay voltage control circuit for receiving said at least one fast/slow input signal and producing at least one control voltage to said voltage controlled delay line in response thereto, said delay voltage control circuit operative to control a level of said at least one control voltage such that a difference between successive levels in said control voltage level increases as said control voltage levels become greater and decreases as said control voltage levels become lower, wherein said at least one fast/slow input signal comprises separate “fast” and “slow” input signals and wherein said delay voltage control circuit comprises: first, second, third and fourth series coupled switching devices having a first circuit node thereof and coupled between a supply voltage line and a reference voltage line, each of said series coupled switching devices including a control terminal thereof, said separate “fast” and “slow” input signals being respectively coupled to said control terminal of said first and fourth switching devices and said control terminal of said third switching device being coupled to said first circuit node intermediate said second and third switching devices to provide said at least one control voltage; and fifth and sixth series coupled switching devices having a second circuit node therebetween and coupled between said supply voltage line and said reference voltage line, each of said fifth and sixth switching devices including a control terminal thereof, said control terminal of said sixth switching device being coupled to said first circuit node to provide a first control voltage and said control terminal of said fifth switching device being coupled to said control terminal of said second switching device and to said second circuit node to provide a second control voltage.

Claim 23

The circuit of claim 18 wherein said first, second, third, fourth, fifth and sixth switching devices are MOS transistors.

Claim 24

The circuit of claim 19 wherein said first, second and fifth switching devices comprise P-channel MOS transistors and said third, fourth and sixth switching devices comprise N-channel MOS transistors.

Claim 25

The circuit of claim 19 wherein as said at least one control voltage decreases, a gate-to-source voltage of said third switching device decreases.