Patent US20040004244A1 successfully refreshed from Google Patents.
US20040004244A1
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Structures, methods, and systems for ferroelectric memory transistors
Assignee: Micron Technology Inc
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Filing: 2003-06-20
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Granted: —
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Expires: 2023-06-20
Abstract
Abstract Integrated memory circuits, key components in thousands of electronic and computer products, have recently been made using ferroelectric memory transistors, which offer faster write cycles and lower power requirements than over conventional floating-gate transistors. One problem that hinders the continued down-scaling of conventional ferroelectric memory transistors is the vulnerability of their gate insulations to failure at thinner dimensions. Accordingly, the inventors devised unique ferroelectric gate structures, one of which includes a high-integrity silicon-oxide insulative layer, a doped titanium-oxide layer, a weak-ferroelectric layer, and a control gate. The doped titanium-oxide layer replaces a metal layer in the conventional ferroelectric gate structure, and the weak-ferroelectric layer replaces a conventional ferroelectric layer. These replacements reduce the permittivity mismatch found in conventional gate structures, and thus reduce stress on gate insulation layers, thereby improving reliability of ferroelectric memory transistors, particularly those with thinner gate insulation.
Inventors
- 👤 Kie Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:46
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/689; H10D30/00; H10D30/60; H10D30/701; H10D64/01; H10D64/031; H10D64/033; H10B; H10B53/00
Claims Analysis
Total Claims: 56
Claim 1
Independent Claim
55 words
1 . A ferroelectric memory transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 2
Dependent Claim
55 words
1 . A ferroelectric memory transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 3
Dependent Claim
17 words
2 . The transistor of claim 1 , wherein the ferroelectric layer is a weak ferroelectric layer.
Claim 4
Dependent Claim
19 words
3 . The transistor of claim 1 , wherein the ferroelectric layer has a dielectric constant less than 1000.
Claim 5
Dependent Claim
31 words
4 . The transistor of claim 1 , wherein the ferroelectric layer is characterized by a spontaneous polarization within a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 .
Claim 6
Dependent Claim
30 words
5 . The transistor of claim 1 , wherein the doped insulative layer has a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 7
Dependent Claim
44 words
6 . The transistor of claim 1 , wherein the first insulative layer has a dielectric constant of about 4, the doped insulative layer has a dielectric constant of about 165 or 180, and the ferroelectric layer has a dielectric constant of about 250.
Claim 8
Dependent Claim
19 words
7 . The transistor of claim 1 , wherein the first insulative layer consists essentially of a silicon oxide.
Claim 9
Dependent Claim
23 words
8 . The transistor of claim 1 , wherein the doped insulative layer comprises at least one of strontium- or barium-doped titanium oxide.
Claim 10
Dependent Claim
37 words
9 . The transistor of claim 1 , wherein the ferroelectric layer consists essentially of zinc oxide doped with lithium at a level of about 1 mol percent to about 30 mol percent of the metal component.
Claim 11
Dependent Claim
37 words
10 . The transistor of claim 1 , wherein the ferroelectric layer consists essentially of zinc oxide doped with magnesium at a level of about 1 mol percent to about 30 mol percent of the metal component.
Claim 12
Dependent Claim
74 words
11 . A ferroelectric memory transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization in a range of approximately 0.01 micro-Coulomb/cm 2 to 1 microCoulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the weak ferroelectric layer.
Claim 13
Dependent Claim
74 words
11 . A ferroelectric memory transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization in a range of approximately 0.01 micro-Coulomb/cm 2 to 1 microCoulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the weak ferroelectric layer.
Claim 14
Dependent Claim
94 words
12 . A ferroelectric memory transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization in a range of approximately 0.01 micro-Coulomb/cm 2 to 1 microCoulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the ferroelectric layer, the doped insulative layer having a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 15
Dependent Claim
94 words
12 . A ferroelectric memory transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization in a range of approximately 0.01 micro-Coulomb/cm 2 to 1 microCoulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the ferroelectric layer, the doped insulative layer having a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 16
Dependent Claim
49 words
13 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a strontium-doped titanium-oxide layer on the silicon-oxide layer; a doped zinc-oxide layer on the doped titanium-oxide layer; a gate conductor on the zinc-oxide layer
Claim 17
Dependent Claim
49 words
13 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a strontium-doped titanium-oxide layer on the silicon-oxide layer; a doped zinc-oxide layer on the doped titanium-oxide layer; a gate conductor on the zinc-oxide layer
Claim 18
Dependent Claim
50 words
14 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a strontium-doped titanium-oxide layer on the silicon-oxide layer; a lithium-doped zinc-oxide layer on the doped titanium-oxide layer; a gate conductor on the lithium-doped zinc-oxide layer.
Claim 19
Dependent Claim
50 words
14 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a strontium-doped titanium-oxide layer on the silicon-oxide layer; a lithium-doped zinc-oxide layer on the doped titanium-oxide layer; a gate conductor on the lithium-doped zinc-oxide layer.
Claim 20
Dependent Claim
50 words
15 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a strontium-doped titanium-oxide layer on the silicon-oxide layer; a magnesium-doped zinc-oxide layer on the doped titanium-oxide layer; a gate conductor on the magnesium-doped zinc-oxide layer.
Claim 21
Dependent Claim
50 words
15 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a strontium-doped titanium-oxide layer on the silicon-oxide layer; a magnesium-doped zinc-oxide layer on the doped titanium-oxide layer; a gate conductor on the magnesium-doped zinc-oxide layer.
Claim 22
Dependent Claim
50 words
16 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a barium-doped titanium-oxide layer on the silicon-oxide layer; a doped zinc-oxide layer on the barium-doped titanium-oxide layer; and a gate conductor on the zinc-oxide layer.
Claim 23
Dependent Claim
50 words
16 . A ferroelectric memory transistor comprising: a silicon substrate having a desired channel conduction region; a silicon-oxide layer over the desired channel conduction region; a barium-doped titanium-oxide layer on the silicon-oxide layer; a doped zinc-oxide layer on the barium-doped titanium-oxide layer; and a gate conductor on the zinc-oxide layer.
Claim 24
Dependent Claim
67 words
17 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; wherein forming the silicon-oxide layer comprises: establishing a chamber temperature of approximately 400 degrees Celsius; generating oxygen atoms in a Krypton plasma; forming a doped titanium-oxide layer over the silicon-oxide layer; and forming a doped zinc-oxide layer on the titanium-oxide layer.
Claim 25
Dependent Claim
67 words
17 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; wherein forming the silicon-oxide layer comprises: establishing a chamber temperature of approximately 400 degrees Celsius; generating oxygen atoms in a Krypton plasma; forming a doped titanium-oxide layer over the silicon-oxide layer; and forming a doped zinc-oxide layer on the titanium-oxide layer.
Claim 26
Dependent Claim
29 words
18 . The method of claim 17 wherein forming the doped titanium-oxide layer over the silicon-oxide layer comprises: using atomic-layer deposition to form a strontium- or barium-doped titanium-oxide layer.
Claim 27
Dependent Claim
28 words
19 . The method of claim 17 wherein forming the doped titanium-oxide layer over the silicon-oxide layer comprises: using atomic-layer deposition to form a strontium- or barium-titanate layer.
Claim 28
Dependent Claim
111 words
20 . The method of claim 18 , wherein using atomic-layer deposition comprises: establishing an ambient pressure of about 10 mbar within a deposition chamber containing the silicon-oxide layer; establishing an ambient temperature between 250 and 325 degrees Celsius within the deposition chamber; alternately introducing a strontium or barium precursor and a titanium-oxide precursor into the deposition chamber, with the strontium or barium precursor and the titanium-oxide precursors introduced at rates to saturate reactions of the precursors at a surface of the silicon-oxide layer; and introducing water vapor into the deposition chamber concurrent with the introduction of the strontium or barium precursor and concurrent with the introduction of the titanium-oxide precursors.
Claim 29
Dependent Claim
19 words
21 . The method of claim 19 , wherein the strontium or barium precursors consists essentially of cyclopentadienyl compounds.
Claim 30
Dependent Claim
33 words
22 . The method of claim 19 , wherein the strontium or barium precursors consists essentially of Sr(C 5 —I—Pr 3 H 2 ) 2 or Ba(C 5 Me 5 ) 2 .
Claim 31
Dependent Claim
30 words
23 . The method of claim 20 , further comprising: purging the deposition chamber with nitrogen gas between alternate introductions of the strontium or barium precursors and the titaniumoxide precursors.
Claim 32
Dependent Claim
39 words
24 . The method of claim 17 wherein forming the doped zinc-oxide layer comprises: providing a composite mass comprising zinc oxide and particles of lithium or magnesium; and magnetron sputtering matter from the composite mass onto the titaniumoxide layer.
Claim 33
Dependent Claim
28 words
25 . The method of claim 17 wherein forming the doped zinc-oxide layer comprises: jet-vapor deposition of zinc oxide, (lithium carbonate), and magnesium oxide on the titanium-oxide layer.
Claim 34
Dependent Claim
22 words
26 . The method of claim 17 wherein forming the doped zinc-oxide layer comprises: chemical-vapor deposition of zinc-oxide on the titanium-oxide layer.
Claim 35
Dependent Claim
123 words
27 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; forming a doped titanium-oxide layer over the silicon-oxide layer, wherein forming the doped titanium-oxide layer comprises establishing an ambient pressure of about 10 mbar within a deposition chamber containing the silicon-oxide layer; establishing an ambient temperature between 250 and 325 degrees Celsius within the deposition chamber; alternately introducing a dopant precursor and a titanium-oxide precursor into the deposition chamber; and introducing water vapor into the deposition chamber concurrent with the introduction of the strontium or barium precursor and concurrent with the introduction of the titanium-oxide precursors; and forming a doped zinc-oxide layer on the doped titanium-oxide layer.
Claim 36
Dependent Claim
123 words
27 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; forming a doped titanium-oxide layer over the silicon-oxide layer, wherein forming the doped titanium-oxide layer comprises establishing an ambient pressure of about 10 mbar within a deposition chamber containing the silicon-oxide layer; establishing an ambient temperature between 250 and 325 degrees Celsius within the deposition chamber; alternately introducing a dopant precursor and a titanium-oxide precursor into the deposition chamber; and introducing water vapor into the deposition chamber concurrent with the introduction of the strontium or barium precursor and concurrent with the introduction of the titanium-oxide precursors; and forming a doped zinc-oxide layer on the doped titanium-oxide layer.
Claim 37
Dependent Claim
15 words
28 . The method of claim 27 wherein the dopant precursor includes strontium or barium.
Claim 38
Dependent Claim
77 words
29 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; forming a doped titanium-oxide layer over the silicon-oxide layer; and forming a doped zinc-oxide layer on the titanium-oxide layer, wherein forming the doped zinc-oxide layer comprises: providing a composite mass comprising zinc oxide and particles of lithium or magnesium; and magnetron sputtering matter from the composite mass onto the titanium-oxide layer.
Claim 39
Dependent Claim
77 words
29 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; forming a doped titanium-oxide layer over the silicon-oxide layer; and forming a doped zinc-oxide layer on the titanium-oxide layer, wherein forming the doped zinc-oxide layer comprises: providing a composite mass comprising zinc oxide and particles of lithium or magnesium; and magnetron sputtering matter from the composite mass onto the titanium-oxide layer.
Claim 40
Dependent Claim
69 words
30 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; forming a doped titanium-oxide layer over the silicon-oxide layer; and forming a doped zinc-oxide layer on the titanium-oxide layer, wherein forming the doped zinc-oxide layer comprises: jet-vapor deposition of zinc oxide in combination with lithium carbonate or magnesium oxide on the titanium-oxide layer.
Claim 41
Dependent Claim
69 words
30 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate; forming a doped titanium-oxide layer over the silicon-oxide layer; and forming a doped zinc-oxide layer on the titanium-oxide layer, wherein forming the doped zinc-oxide layer comprises: jet-vapor deposition of zinc oxide in combination with lithium carbonate or magnesium oxide on the titanium-oxide layer.
Claim 42
Dependent Claim
176 words
31 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate, wherein forming the silicon-oxide layer comprises: establishing a chamber temperature of approximately 400 degrees Celsius; generating oxygen atoms in a Krypton plasma; forming a doped titanium-oxide layer over the silicon-oxide layer, wherein forming the doped titanium-oxide layer comprises: establishing an ambient pressure of about 10 mbar within a deposition chamber containing the silicon-oxide layer; establishing an ambient temperature between 250 and 325 degrees Celsius within the deposition chamber; alternately introducing a dopant precursor and a titanium-oxide precursor into the deposition chamber; and introducing water vapor into the deposition chamber concurrent with the introduction of the strontium or barium precursor and concurrent with the introduction of the titanium-oxide precursors; and forming a doped zinc-oxide layer on the titanium-oxide layer, wherein forming the doped zinc-oxide layer comprises: providing a composite mass comprising zinc oxide and particles of lithium or magnesium; and magnetron sputtering matter from the composite mass onto the titanium-oxide layer.
Claim 43
Dependent Claim
176 words
31 . A method for making a ferroelectric memory transistor, the method comprising: forming a silicon-oxide layer over a desired channel region of a silicon substrate, wherein forming the silicon-oxide layer comprises: establishing a chamber temperature of approximately 400 degrees Celsius; generating oxygen atoms in a Krypton plasma; forming a doped titanium-oxide layer over the silicon-oxide layer, wherein forming the doped titanium-oxide layer comprises: establishing an ambient pressure of about 10 mbar within a deposition chamber containing the silicon-oxide layer; establishing an ambient temperature between 250 and 325 degrees Celsius within the deposition chamber; alternately introducing a dopant precursor and a titanium-oxide precursor into the deposition chamber; and introducing water vapor into the deposition chamber concurrent with the introduction of the strontium or barium precursor and concurrent with the introduction of the titanium-oxide precursors; and forming a doped zinc-oxide layer on the titanium-oxide layer, wherein forming the doped zinc-oxide layer comprises: providing a composite mass comprising zinc oxide and particles of lithium or magnesium; and magnetron sputtering matter from the composite mass onto the titanium-oxide layer.
Claim 44
Dependent Claim
81 words
32 . A system comprising: at least one processor; and a memory device coupled to the one processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 45
Dependent Claim
81 words
32 . A system comprising: at least one processor; and a memory device coupled to the one processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 46
Dependent Claim
19 words
33 . The system of claim 32 , wherein the ferroelectric layer has a dielectric constant less than 1000.
Claim 47
Dependent Claim
31 words
34 . The system of claim 33 , wherein the ferroelectric layer is characterized by a spontaneous polarization in a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 .
Claim 48
Dependent Claim
30 words
35 . The system of claim 33 , wherein the doped insulative layer has a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 49
Dependent Claim
19 words
36 . The system of claim 33 , wherein the first insulative layer consists essentially of a silicon oxide.
Claim 50
Dependent Claim
23 words
37 . The system of claim 33 , wherein the doped insulative layer comprises at least one of strontium- or barium-doped titanium oxide.
Claim 51
Dependent Claim
37 words
38 . The system of claim 33 , wherein the ferroelectric layer consists essentially of zinc oxide doped with magnesium at a level of about 1 mol percent to about 30 mol percent of the metal component.
Claim 52
Dependent Claim
99 words
39 . A system comprising: at least one processor; and a memory device coupled to the one processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization within a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 53
Dependent Claim
99 words
39 . A system comprising: at least one processor; and a memory device coupled to the one processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization within a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 54
Dependent Claim
30 words
40 . The system of claim 39 , wherein the doped insulative layer has a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 55
Dependent Claim
19 words
41 . The system of claim 39 , wherein the first insulative layer consists essentially of a silicon oxide.
Claim 56
Dependent Claim
23 words
42 . The system of claim 39 , wherein the doped insulative layer comprises at least one of strontium- or barium-doped titanium oxide.
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