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JPS6414938A Expired / Lapsed JP ⏱️ 0.0 years remaining

Forming method of multilayered interconnection

Assignee: NEC Corp
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Filing: 1987-07-08
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Granted: —
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Expires: 2007-07-08
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Abstract

Abstract PURPOSE:To implement a minute multilayered interconnection using conductive macromolecules, by forming grooves in a second wiring pattern in a flattened insulating film on a first metal wiring on a semiconductor substrate, connecting the first layer with a through hole, forming e conductive macromolecular film on the entire surface, etching the entire surface, and flattening the surface. CONSTITUTION:A first wiring 13, which has a plurality of Al wirings each having a thickness of about 1.2mum and a width of about 1.0mum, is formed on a semiconductor substrate 11 through an insulating film 12. An interlayer insulating film 14 is formed on the first wiring 13 to a thickness of about 3.5mum from the surface of the insulating film 12. The surface of the interlayer insulating film 14 is flattened by a CVD method and the like. Grooves 16 having a depth of about 1.5mum are etched tn the interlayer insulating film 14 by using the inverted pattern of a second wiring. A through hole 17 is opened at a specified position. Conductive macromolecular solution is applied by rotation. Baking is performed at an appropriate temperature, and a conductive macromolecular film 15 is formed. Then, the entire surface of the conductive macromolecular film 15 is etched so that the film remains only at the groove parts. Thus the second wiring is formed.

Inventors

  • 👤 Akira Isobe

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 21:34
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS60148149A Cited
JPS61287147A Cited

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