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JPS5944843A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Mitsubishi Electric Corp
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Filing: 1982-09-07
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Granted: —
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Expires: 2002-09-07
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Abstract

Abstract PURPOSE:To improve integration density by forming adjacent P type and N type transistors with a gate interval widened. CONSTITUTION:The P type transistors 11, 13 and N type transistors 12, 14 which operate as complementary internal logic function elements are adjacently constituted in vertical. Thease gates are connected to the other parts through contacts 56, 57, 65, 66. Since interval of gates of transistors 11-14 are widened, wiring patterns do not occur short-circuitting even when these transistors are driven by different voltages. Accordingly, it is no longer necessary to provide an empty region on a chip and thereby integration density can be improved.

Inventors

  • 👤 Hiroichi Ishida
  • 👤 博一 石田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 18:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5745948A Cited
JPS58190036A Cited

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