Gate array large scale integrated circuit device

Abstract

Abstract PURPOSE:To efficiently form a test circuit of internal cell array region and a desired circuit such as the Schmidt circuit and the clock gate circuit etc. within the relevant region by providing general purpose cell array region adjacent to the peripheral circuit region. CONSTITUTION:The regular C-MOS gate array 5 is arranged in both sides of wiring region 6 in the internal cell array region 2. The peripheral circuit region 3 is composed of the transistor region 7 where transistors which form the interface circuit for outside of LSI and protection circuit such as an input buffer circuit, output buffer circuit, two-way buffer circuit etc. and the region where input/output pads 8 are arranged. In the general purpose cell array region 4, MOS transistor array is provided and the shaded region is prepare for forming a desired circuit such as the Schmidt trigger circuit or clock gate circuit, independent of the circuit in the peripheral circuit region. The transistors in the area indicated by X marks forms an output buffer circuit or two-way buffer circuit in combination with the transistors in the adjacent peripheral circuit region.

Inventors

• 👤 Nobutake Matsumura
• 👤 松村　信威
• 👤 Shinji Sato
• 👤 佐藤　眞司

Bibliographic Details