Dma transfer system for a plurality of words

Abstract

Abstract PURPOSE:To perform direct memory access in an optimum speed for various I/O devices, by changing the word length of data making direct memory access transfer. CONSTITUTION:A CPU 1 has data input/output terminals D0-7 in 8-bit and address data output terminals A0-16 in 16-bit and is connected to a data bus 2 and an address bus 3 in 16-bit. Similarly, a direct memory access control device DMAC 4 has data input terminals D0-7 in 8-bit and address data output terminals A0-16 in 16-bit and is connected with the buses 2 and 3 and a control signal is received and given between the CPU 1 and the DMAC 4. Through the designation of the software, the number of words of data can be selected for 4, 8 and 16-bit and under the control of the DMAC 4, signals in 8 and 16-bit can be combined and outputted from the CPU 1.

Inventors

• 👤 Junichi Komuro
• 👤 純一 小室

Bibliographic Details