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JPS5555489A Expired / Lapsed JP ⏱️ 0.0 years remaining

Data processing system

Assignee: Sanyo Electric Co Ltd
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Filing: 1978-10-19
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Granted: —
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Expires: 1998-10-19
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Abstract

Abstract PURPOSE:To make it possible to handle data having an integral multiple length of the bit length of one address area by selecting simultaneously a main area and a sub-area by one address designation. CONSTITUTION:When mode controller 8 is operated, a high-level signal is applied to exclusive OR gate 7, and prescribed-bit signals of an address are changed not only to select memory chips 100... of a main area according to the address by chip selector 3 but also to select memory chips 200... of a sub-area through selector 4 by a converted address where prescribed-bit signals are changed. Consequently, data having an integral multiple length of the bit length of one address length can be handled to make data processing high-speed.

Inventors

  • 👤 Masayuki Iida

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 09:33
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12

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