Patent GB2139019A successfully refreshed from Google Patents.
GB2139019A
Expired / Lapsed
GB
⏱️ 0.0 years remaining
Printed circuit board testers
Assignee: The General Electric Company PLC
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Filing: 1984-04-06
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Granted: —
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Expires: 2004-04-06
Abstract
Abstract To reduce the cost of a different probe array for every kind of PCB (10) to be tested each test node connection of a tester is permanently wired to a single ended probe (5,5',5'') on a jig (1,2) having a standard probe pattern. A double ended probe array (11) is arranged to connect board test nodes with a circuit board pattern (6) which is then contacted by the single ended probe pattern. Since the double ended probes are recoverable the items per PCB type to be tested are the circuit board (6) and the plate (12) containing the board probe pattern. Alternatively the plate (12) may have a grid pattern for probes, only those probes required for a particular PCB type to be tested being fitted. <IMAGE>
Inventors
- 👤 Dennis Roger Vernon
- 👤 James Anthony Walsh
Bibliographic Details
Application Number
—
Jurisdiction
GB
Data Source
google_patents
Last Synchronized
2026-11-01 11:53
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07364; G01R1/07378
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
266 words
A connection interface for interconnecting inputs and/or outputs of test equipment with test nodes of a printed circuit board to be tested, wherein a removeable interconnection board of electricallyinsulating material carries a first plurality of contacts in a pattern which substantially mirrors a pattern of test nodes of a printed circuit board to be tested, each of said first plurality of contacts is electrically connected to a respective one of a second plurality of contacts which are also carried on said removable interconnection board and which form a respective pattern spaced apart from the pattern of the first plurality of contacts, a first plurality of electricallyconducting probes is mounted in a first electricallyinsulating board in a pattern such that one end of each probe contacts a respective one of said first plurality of contacts whilst the opposed ends of the probes present a pattern of contacts for connection to test nodes of a printed circuit board under test, a second plurality of electrically-conducting probes is mounted in at least one second electricallyinsulating board such that one end of each of the second plurality of probes contacts a respective one of said second plurality of contacts, and the opposed end of each of the second plurality of probes is arranged for electrical connection to a respective input or output of test equipment such that, in use, when a printed circuit board is brought into contact with said pattern of contacts presented by said first plurality of probes each test node thereof is temporarily electrically connected to a respective input or output of test equipment connected as aforesaid.
Claim 2
Dependent Claim
266 words
A connection interface for interconnecting inputs and/or outputs of test equipment with test nodes of a printed circuit board to be tested, wherein a removeable interconnection board of electricallyinsulating material carries a first plurality of contacts in a pattern which substantially mirrors a pattern of test nodes of a printed circuit board to be tested, each of said first plurality of contacts is electrically connected to a respective one of a second plurality of contacts which are also carried on said removable interconnection board and which form a respective pattern spaced apart from the pattern of the first plurality of contacts, a first plurality of electricallyconducting probes is mounted in a first electricallyinsulating board in a pattern such that one end of each probe contacts a respective one of said first plurality of contacts whilst the opposed ends of the probes present a pattern of contacts for connection to test nodes of a printed circuit board under test, a second plurality of electrically-conducting probes is mounted in at least one second electricallyinsulating board such that one end of each of the second plurality of probes contacts a respective one of said second plurality of contacts, and the opposed end of each of the second plurality of probes is arranged for electrical connection to a respective input or output of test equipment such that, in use, when a printed circuit board is brought into contact with said pattern of contacts presented by said first plurality of probes each test node thereof is temporarily electrically connected to a respective input or output of test equipment connected as aforesaid.
Claim 3
Dependent Claim
45 words
A connection interface as claimed in Claim 1, in which said at least one second electrically insulating board is hingeably attached to a frame which has means to locate said interconnection board, said first electrically insulated board and a printed circuit board to be tested.
Claim 4
Dependent Claim
47 words
A connection interface as claimed in Claim 1 or
Claim 2, in which said first electrically insulated board is provided with apertures in a predetermined grid for holding said first plurality of probes, each of said first plurality of probes being fitted to the board as required.
Claim 5
Dependent Claim
51 words
A connection interface as claimed in Claim 1 or
Claim 2, in which said first electrically insulating board is fully equipped with a plurality of part probes on a grid pattern such that fitting of the other part of each of the first plurality of probes is carried out as required.
Claim 6
Dependent Claim
36 words
A connection interface as claimed in any one of Claims 1 to 4, in which each of the probes is spring loaded, the second plurality at one end only and the first plurality at both ends.
Claim 7
Dependent Claim
32 words
A connection interface for interconnecting inputs and/or outputs of test equipment with test nodes of a printed circuit board to be tested, substantially as herein described with reference to the accompanying drawing.
Claim 8
Dependent Claim
32 words
A connection interface for interconnecting inputs and/or outputs of test equipment with test nodes of a printed circuit board to be tested, substantially as herein described with reference to the accompanying drawing.
References Cited (Backward Citations)
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