Patent EP0959411A1 successfully refreshed from Google Patents.
EP0959411A1
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Packet distribution in a microcomputer
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1999-04-27
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Granted: —
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Expires: 2019-04-27
Abstract
Abstract An integrated circuit device (11) with an address and data path (15) interconnects a CPU (12) with at least one module (14) and a memory interface (32), the module (14) having circuitry (8) to generate an event request packet and the CPU having event logic (44) to decode the packet as well as circuitry to generate addressed memory access packets, the same address and data path (15) being used for the distribution of event request packets and memory access packets. <IMAGE>
Inventors
- 👤 Andrew Michael Jones
- 👤 Michael David May
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
99 words
A computer system including an integrated circuit chip with
an address and data path interconnecting a plurality of on-chip
devices including at least one CPU, at least one module and a
memory interface, (a) said module having packet generating
circuitry responsive to an event to generate an event request
packet including a destination address, (b) said CPU having event
logic to decode the packet and identify the request of the
packet, and circuitry to generate addressed memory access
packets, and (c) said address and data path being used for
distribution of both event request packets and memory access
packets.
Claim 2
Dependent Claim
40 words
A computer system according to claim 1 in which both said
module and said CPU each include packet generating circuitry
operable to generate both event request packets and memory access
packets for distribution on the common address and data path.
Claim 3
Dependent Claim
40 words
A computer system according to claim 1 or claim 2 in which
the packet generating circuitry is responsive to receipt of an
event request packet to generate an addressed response bit packet
for distribution on said address and data path.
Claim 4
Dependent Claim
47 words
A computer system according to any one of the preceding
claims in which the packet generating circuitry of a module
includes means to indicate the address of the destination for the
packet as well as the address of the module acting as a source
of the packet.
Claim 5
Dependent Claim
51 words
A computer system according to claim 4 in which the packet
generating circuitry is responsive to receipt of an event request
packet to determine from the packet a source address of the
packet and to generate a response packet using said source
address as the destination indicator for the response packet.
Claim 6
Dependent Claim
30 words
A computer system according to any one of the preceding
claims including an on-chip memory, said memory interface
providing connection between said address and data path and said
on-chip memory.
Claim 7
Dependent Claim
34 words
A computer system according to any one of the preceding
claims including an off-chip memory, said chip having an external
memory interface connected to said off-chip memory and to said
address and data path.
Claim 8
Dependent Claim
62 words
A computer system according to any one of the preceding
claims in which the packet generating circuitry of said module
is arranged to generate an event request packet forming an
interrupt request with a priority indicator and said event logic
of the CPU includes comparator circuitry for comparing priorities
of event request packets received with the priority of any
current CPU activity.
Claim 9
Dependent Claim
42 words
A computer system according to any one of claims 1 to 7 in
which the packet generating circuitry of said module is arranged
to generate an event request packet in the form of a control
packet for control command to the CPU.
Claim 10
Dependent Claim
69 words
A computer system according to any one of the preceding
claims in which a plurality of modules are provided on chip, each
having packet generating circuitry for generating event request
packets, at least one module being arranged to generate event
packets in the form of prioritised interrupt requests and at
least another module being arranged to generate event request
packets in the form of control packets for the CPU.
Claim 11
Dependent Claim
33 words
A computer system according to any one of the preceding
claims in which said address and data path includes at least one
on-chip bus arranged to distribute said packets in bit parallel
format.
Claim 12
Dependent Claim
44 words
A computer system according to claim 10 wherein said
integrated circuit chip includes at least one external port for
off-chip connection, said port including bit format translation
circuitry to convert on-chip packets of bit parallel format to
a less parallel format for transmission off-chip.
Claim 13
Dependent Claim
41 words
A computer system comprising at least two integrated circuit
chips, each as claimed in any one of the preceding claims, the
two chips being connected through external ports to allow
communication between the address and data paths of the
interconnected chips.
Claim 14
Independent Claim
114 words
A method of operating a computer system comprising an
integrated circuit chip with an address and data path
interconnecting a plurality of on-chip devices including at least
one CPU, at least one module and a memory interface, which method
comprises detecting an event at a module, generating an event
request packet with a destination address, distributing the
request packet on the address and data path to the destination,
decoding the packet at the destination to identify the nature of
the request, said method further including generating addressed
memory access packets for memory read and write operations, said
memory access packets and said event request packets being
distributed on the same address and data path.
Claim 15
Dependent Claim
35 words
A method according to claim 14 wherein event request packets
are generated for distribution on the address and data path to
the CPU, which event request packets are in the form of
prioritised interrupt requests.
Claim 16
Dependent Claim
54 words
A method according to claim 14 or claim 15 in which event
request packets are generated for distribution on said address
and data path to the CPU, at least some of said event request
packets being in the form of control command packets to which the
CPU must respond on receipt of the packet.
References Cited (Backward Citations)
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