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EP0936627A1
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Low voltage non volatile memory sense amplifier
Assignee: STMicroelectronics SRL
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Filing: 1998-02-13
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Granted: —
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Expires: 2018-02-13
Abstract
Abstract Sense amplifier circuit for non-volatile memories, of the type apt to draw a reference current from a reference bitline and a cell current from a cell array bitline, and compare them by means of current-voltage converting means and an amplifying stage, said current-voltage converting means comprising also fixing means of a determined voltage on the reference bitline and on the cell array bitline, load circuit means for the reference bitline and the cell array bitline, current mirror circuits for mirroring the reference current into a input node of the amplifying stage and the cell current into a further input of said amplifying stage. According to the invention the load circuit means of the reference bitline (BLREF) and the mirroring means (MR) of the reference current are different circuits and the reference bitline load circuit means are represented by a transistor (P3) which mirrors a predetermined current (IP), generated outside of the sense amplifier circuit (3), in order to have a lower voltage drop on said load circuit means (P3).
Inventors
- 👤 Maurizio Gaibotti
- 👤 Nicolas Demange
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 11:25
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/24; G11C16/26; G11C16/28; G11C7/00; G11C7/06; G11C7/062; G11C7/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
Sense amplifier circuit for non-volatile memories, of the type apt to draw a reference current
from a reference bitline and a cell current from a cell array bitline, and compare them by means of
current-voltage converting means and an amplifying stage, said current-voltage converting means
comprising also fixing means fixing of a determined voltage on the reference bitline and on the cell
array bitline, load circuit means for the reference bitline and the cell array bitline, current mirror
circuits for mirroring the reference current into a input node of the amplifying stage and the cell
current into a further input of said amplifying stage, characterized in that the load circuit means of
the reference bitline (BLREF) and the mirroring means (MR) of the reference current are different
circuits and that the reference bitline load circuit means are represented by a transistor (P3) which
mirrors a predetermined current (IP), generated outside of the sense amplifier circuit (3), in order
to have a lower voltage drop on said load circuit means (P3).
Claim 2
Dependent Claim
96 words
Sense amplifier circuit for non-volatile memories, according to claim 1, characterized in that the
load circuit means (P3) of the reference bitline (BLREF) input the predetermined current (IP) into
a connecting node (DREF) between the fixing means of a determined voltage (N1, INV1) onto
the reference bitline (BLREF) and the mirroring means (MR) of the reference current and that,
between the means fixing a determined voltage (N1, INV1) onto the reference bitline (BLREF)
and the mirroring means (MR) of the reference current, there are provided current compensation
circuits (MR2, MR1', MR3) of said predetermined current (IP).
Claim 3
Dependent Claim
28 words
Sense amplifier circuit for non-volatile memories, according to claim 2, characterized in that
said current compensation circuits (MR2, MR1', MR3) are realized by means of current mirror
circuits.
Claim 4
Dependent Claim
45 words
Sense amplifier circuit for non-volatile memories, according to claim 3, characterized in that the
load circuit means of the reference bitline (MR1) are realized by means of a branch of a current
mirror and that in the other branch the predetermined current (IP) is injected.
Claim 5
Dependent Claim
31 words
Sense amplifier circuit for non-volatile memories, according to one or more of the preceding
claims, characterized in that the current transfer means (MR1', MR2) have a mirroring ratio
different from one.
Claim 6
Dependent Claim
121 words
Method for sensing the current of a memory cell in non-volatile memories, of the type wherein
the comparison is made of the current coming from a line connected to one or more reference
cells with the current coming from a line connected to the memory cell, defining, by means of
biasing means and load means, a voltage dependent from the current on respective nodes of said
line, and comparing, by means of comparator means connected to mirroring means, in turn
connected to said lines, said voltage on said nodess, characterized in that second mirroring means
of the reference current are provided (MR2, MR1, MR1', MR3), apt to separate the biasing (N1,
INV1) and load (P4) means from the mirroring means (MR).
Claim 7
Dependent Claim
77 words
Method for sensing the current of a memory cell in non-volatile memories, according to claim
6, characterized by the fact of a) adding a determined external current (IP) to the reference current (IREF) coming from the
biasing means (N1, INV1); b) providing current compensation means (MR2, MR1', MR3) apt to supply to the mirroring
means (MR) the reference current (IREF) adding to the current (IP+IREF), obtained in step a), a
current proportional to said determined current (IP).
Claim 8
Dependent Claim
84 words
Method for sensing the current of a memory cell in non-volatile memories, according to claim
7, characterized by the fact of a) drawing the reference current generated by two reference cells; b) adding a determined external current to the reference current; c) dividing by two the current obtained in step b), by means of the said current compensation
means, and adding thereto a half of the said determined external current in order to obtain a mean
value of current supplied by the reference cells.
References Cited (Backward Citations)
FR2623932A1
Cited
EP0814484A1
Cited
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