EP0814484A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Nonvolatile memory with a single-cell reference signal generating circuit for reading memory cells
Assignee: STMicroelectronics SRL
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Filing: 1996-06-18
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Granted: —
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Expires: 2016-06-18
Abstract
Abstract A nonvolatile memory (35) presenting a data memory array (2) including memory cells 85); a read circuit (40) including a plurality of sense amplifiers (10), each connected to a respective array branch (17) to be connected to the memory cells; and a reference generating circuit (55) including a single reference cell (60) arranged outside the data memory array (2) and generating a reference signal (I R ). The reference generating circuit (55) presents a plurality of reference branches (41), each connected to a respective sense amplifier (10); and current mirror circuits (53, 54, 62, 63) interposed between the reference cell (60) and the reference branches (41), and supplying the reference branches with the reference signal (I R ).
Inventors
- 👤 Giovanni Campardo
- 👤 Rino Micheloni
- 👤 Stefano Commodaro
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 01:37
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
131 words
A nonvolatile memory (35) comprising a data memory array (2) including memory cells (5); a read circuit (40) comprising a plurality of sense amplifiers (10), each connected to a respective array branch (17) for connection to said memory cells; and a reference generating circuit (55; 70) comprising a reference cell (60) arranged outside said data memory array (2) for generating a reference signal (I R ); characterized in that said reference generating circuit (55; 70) comprises a plurality of reference branches (41), each connected to a respective sense amplifier (10), and connection means (54, 61-64; 72-106) interposed between said reference cell (60) and said reference branches (41) for supplying said reference branches with a first operating signal (I 2 , I C ) correlated to said reference signal (I R ).
Claim 2
Dependent Claim
20 words
A memory as claimed in Claim 1, characterized in that said connection means (54, 61-64; 72-106) comprises current mirror means.
Claim 3
Dependent Claim
82 words
A memory as claimed in Claim 1 or 2, characterized by a first (62, 63; 79, 80) and a second (53, 54; 84, 86) current mirror circuit; said first current mirror circuit having a control input connected to said reference cell, and an output; and said second current mirror circuit comprising a control element (54; 84) connected to said output of said first current mirror circuit (62, 63; 79, 80), and a mirroring element (53; 86) connected to said reference branches (41).
Claim 4
Dependent Claim
168 words
A memory as claimed in Claim 3, characterized in that said first current mirror circuit (62, 63; 79, 80) comprises a first (62; 79) and a second (63; 80) transistor, said first transistor (62; 79) being diode-connected, being interposed between a first reference potential line (42) and said reference cell (60), and having a control terminal, and said second transistor (63; 80) being connected between said first reference potential line (42) and said second current mirror circuit (53, 54; 84, 86), and having a control terminal connected to said control terminal of said first transistor; in that said control element comprises a diode-connected third transistor (54; 84) interposed between a second reference potential line and said second transistor, and having a control terminal; and in that said mirroring element comprises a fourth transistor (53; 86) having a first terminal connected to said second reference potential line, a second terminal connected to said reference branches (41), and a control terminal connected to said control terminal of said third transistor.
Claim 5
Dependent Claim
25 words
A memory as claimed in Claim 4, characterized by predictive equalizing means (81, 91-106) interposed between said fourth transistor (86) and said reference branches (41).
Claim 6
Dependent Claim
177 words
A memory as claimed in Claim 5, characterized in that said predictive equalizing means comprises a fifth transistor (81) current-mirror-connected to said first transistor (79) and interposed between said first reference potential line (42) and said fourth transistor (86); a sixth transistor (93) connected between said first reference potential line and said fourth transistor (86); a seventh transistor (94) current-mirror-connected to said sixth transistor (93); an eighth transistor (96) interposed between said seventh transistor (94) and said second reference potential line; a ninth transistor (97) current-mirror-connected to said eighth transistor (96); a tenth transistor (89) current-mirror-connected to said third transistor (84); an eleventh transistor (91) connected between said first reference potential line and said tenth transistor (89); a twelfth transistor (104) current-mirror-connected to said eleventh transistor (91) and interposed between said first reference potential line and said ninth transistor; a thirteenth transistor (106) connected between said twelfth transistor (104) and said second reference potential line; and a plurality of fourteenth transistors (107) current-mirror-connected to said thirteenth transistor (106) and each connected to a respective reference branch (41).
Claim 7
Dependent Claim
54 words
A memory as claimed in Claim 6, characterized in that said first (79), second (80), fifth (81), sixth (93), seventh (94), eleventh (91) and twelfth (104) transistors are PMOS transistors; and in that said third (84), fourth (86), eighth (96), ninth (97), tenth (89), thirteenth (106) and fourteenth (107) transistors are native NMOS transistors.
Claim 8
Dependent Claim
117 words
A memory as claimed in Claim 1 or 2, characterized in that said connection means comprises generating means (84, 86) connected to said reference cell and generating a second operating signal (I M ) correlated to said reference signal (I R ) and presenting an error; first subtracting means (81, 92, 93) connected to said reference cell (60) and to said first generating means (84, 86) and generating an error signal (I D ) proportional to said error; and second subtracting means (97, 100, 104) connected to said first subtracting means and to said generating means, and generating said first operating signal (I C ) as the difference between said second operating signal and said error signal.
Claim 9
Dependent Claim
40 words
A memory as claimed in any one of the foregoing Claims, characterized by a reference memory array (71) separated from said data memory array (2); and in that said reference memory cell (60) forms part of said reference memory array.
References Cited (Backward Citations)
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