Patent EP0843361A1 successfully refreshed from Google Patents.
EP0843361A1
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EP
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Memory device
Assignee: Hitachi Ltd
•
Filing: 1997-11-12
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Granted: —
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Expires: 2017-11-12
Abstract
Abstract A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3nm thickness and layers (15) of Si 3 N 4 of 1nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
Inventors
- 👤 Kazuo Nakazato
- 👤 Kiyoo Itoh
- 👤 Hiroshi Mizuta
- 👤 Toshihiko Sato
- 👤 Toshikazu Shimada
- 👤 Haroon Ahmed
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:04
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C13/00; G11C13/0002; G11C13/0009; G11C13/0014; G11C13/02; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/688; H10D64/01342; H10D64/01346; H10D64/0135; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/691
Claims Analysis
Total Claims: 61
Claim 1
Independent Claim
95 words
A memory device comprising a path (4) for charge carriers, a node (1, 30, 36,
44) for storing charge to produce a field which alters the conductivity of the path, and
a tunnel barrier configuration (2) through which charge carriers tunnel in response to
a given voltage so as to become stored on the node, the tunnel barrier configuration
exhibiting an energy band profile that comprises a dimensionally relatively wide
barrier component (17) with a relatively low barrier height, and at least one
dimensionally relatively narrow barrier component (18) with a relatively high barrier
height.
Claim 2
Dependent Claim
33 words
A memory device according to claim 1 wherein the component (18) of the
energy band profile of relatively high barrier height is provided by an element of a
width of 3nm or less.
Claim 3
Dependent Claim
30 words
A memory device according to claim 1 or 2 wherein the energy band profile
of the tunnel barrier configuration includes a plurality of said relatively high barrier
height components (18).
Claim 4
Dependent Claim
20 words
A memory device according to any preceding claim wherein the barrier
configuration comprises a multiple tunnel junction configuration (15, 16).
Claim 5
Dependent Claim
51 words
A memory device according to claim 3 or 4 wherein the configuration (15, 16)
includes alternate layers of relatively electrically conductive and insulating material
wherein the layers collectively provide said relatively low barrier height component
of the energy band profile, and the individual insulating layers provide the relatively
high barrier components.
Claim 6
Dependent Claim
19 words
A memory device according to claim 5 wherein the alternate layers (15, 16)
comprise polysilicon and silicon nitride respectively.
Claim 7
Dependent Claim
37 words
A memory device according to claim 5 or 6 wherein the electrically
conductive layers each are of a thickness of less than 10 nm and the insulating layers
are of a thickness of the order of 2nm.
Claim 8
Dependent Claim
21 words
A memory device according to claim 1, 2 or 3 wherein the barrier
configuration comprises a Schottky barrier configuration (16, 28).
Claim 9
Dependent Claim
22 words
A memory device according to claim 8 wherein the configuration includes
alternate layers (16, 18) of electrically conductive material and semiconductor
material.
Claim 10
Dependent Claim
28 words
A memory device according to any preceding claim wherein the charge
storage node comprises a layer (1) of electrically conductive material between the
barrier configuration and said path.
Claim 11
Dependent Claim
15 words
A memory device according to claim 10 wherein the layer (1) comprises doped
semiconductor material.
Claim 12
Dependent Claim
23 words
A memory device according to any preceding claim wherein the charge
storage node comprises a plurality of conductive islands (30, 36, 44, 68).
Claim 13
Dependent Claim
19 words
A memory device according to claim 12 wherein the islands (30, 36, 44) are
distributed in the barrier configuration.
Claim 14
Dependent Claim
18 words
A memory device according to claim 13 wherein the islands have a diameter
of 5 nm or less.
Claim 15
Dependent Claim
30 words
A memory device according to claim 13 or 14 wherein the islands give rise to
relatively narrow, low barrier components of said energy band profile between said
relatively high components.
Claim 16
Dependent Claim
28 words
A memory device according to claim 12, 13, 14 or 15 wherein the islands are
arranged in layers (30, 46, 47) separated by electrically insulating material (29, 30).
Claim 17
Dependent Claim
18 words
A memory device according to claim 16, wherein the spacing of the layers is
less than 3 nm.
Claim 18
Dependent Claim
30 words
A memory device according to claim 17 wherein the islands have a diameter
of the order of 3nm and the spacing of the layers is of the order of 2nm.
Claim 19
Dependent Claim
20 words
A memory device according to any one of claims 12 to 18 wherein the islands
comprise nano-crystals of semiconductor material.
Claim 20
Dependent Claim
20 words
A memory device according to any one of claims 12 to 18 wherein the islands
are formed of a metal.
Claim 21
Dependent Claim
24 words
A memory device according to claim 20 wherein the metallic islands have
been formed by sputtering and are distributed in an insulating metallic oxide.
Claim 22
Dependent Claim
22 words
A memory device according to any one of claims 12 to 20 wherein the islands
comprise particles deposited from a liquid suspension.
Claim 23
Dependent Claim
59 words
A memory device according to any preceding claim wherein the tunnel barrier
configuration exhibits a blocking voltage range (V B ) in which charge carrier
tunnelling to the node is blocked, and including control means (9, 51, 59 - 61)
operative to increase and decrease the blocking voltage range to control the amount
of charge stored in the node.
Claim 24
Dependent Claim
24 words
A memory device according to claim 23 wherein the charge storage node (1)
is configured to store charge in a plurality of discrete states.
Claim 25
Dependent Claim
38 words
A memory device according to claim 24 wherein the control means (9) is
operative to raise and lower the blocking voltage range so as to permit only a selected
one of the states to exist at the node.
Claim 26
Dependent Claim
25 words
A memory device according to claim 23 or 24 wherein the control means (51)
is operative to vary the width of the voltage blocking range.
Claim 27
Dependent Claim
82 words
A memory device according to any one of claims 23 to 26 wherein the control
means (59-61) is operative to lower the height of the relatively wide barrier
component (17) so that charge tunnels through the or each said relatively narrow
barrier component (18) to become stored in the node, and the control means is
operative to raise height of the relatively wide barrier component (17) so that charge
stored in the node is inhibited from tunnelling through the barrier configuration (2).
Claim 28
Dependent Claim
80 words
A memory device according to claim 27 wherein the control means (59-61) is
operative to apply to the barrier configuration (2) a write voltage (V W ) for causing
charge tunnelling to the node, a read voltage (V R ) greater than the write voltage
(V W ) for permitting data to be read from the device selectively, and a standby voltage
(v SB ) greater than the read voltage (V R ), for inhibiting charge tunnelling from the
node.
Claim 29
Dependent Claim
33 words
A memory device according to any preceding claim including a control
electrode (9) from which charge carriers tunnel through the barrier configuration to
the node in response to a given voltage applied thereto.
Claim 30
Dependent Claim
28 words
A memory device according to a claim 1 or 2 including a single one of said
relatively narrow barrier components (67) with a width wider than 3 nm.
Claim 31
Dependent Claim
31 words
A memory device according to claim 30 wherein said single barrier
component is formed by a layer of Si 3 N 4 (67) sandwiched between layers (52, 53) of
undoped Si.
Claim 32
Dependent Claim
30 words
A memory device according to any preceding claim including a gate electrode
(51) for applying an electric field to the tunnel barrier configuration (2) to alter the
barrier configuration thereof.
Claim 33
Dependent Claim
30 words
A memory device according to any preceding claim wherein the amount of
charge that can be stored on the charge storage node (1) is limited by the Coulomb
blockade effect.
Claim 34
Dependent Claim
19 words
A memory device according to any preceding claim including source and
drain regions (5, 6) coupled to the path.
Claim 35
Dependent Claim
30 words
A plurality of memory devices according to any preceding claim formed as an
array of memory cells (M mn ) in rows (m) and columns (n) in a common substrate.
Claim 36
Dependent Claim
53 words
A memory device according to claim 35 including source and drain lines (S, Y,
5, 6) coupled to the respective paths (4) of the columns of cells, and word lines
extending along the rows of the cells for controlling the tunnelling of charge through
the barrier configurations of the cells (M mn ).
Claim 37
Dependent Claim
31 words
A memory device according to claim 35 or 36 including means (58, 59, 60, 61,
62) for selectively reading stored data from the cells individually, and for refreshing
the stored data.
Claim 38
Dependent Claim
24 words
A memory device according to claim 37 including data writing means (58, 59,
60, 61, 62) for selectively storing data in the cells individually.
Claim 39
Dependent Claim
214 words
A memory device according to claim 35 , 37 or 38 including sensing lines
(S 1 ....S n ) for detecting current flowing in the paths of respective columns of the
memory cells (M mn ), word lines (X 1 ....X m ), data lines (Y 1 ....Y n ) for controlling the
barrier configurations (2) of the memory cells of a respective column thereof, a
precharge circuit (60) for precharging the sensing lines, the sensing lines taking up a
charge level dependent upon the stored charge at the charge storage node (N) of a
particular one of the cells in a column thereof read in response to a read voltage (V R )
applied to a corresponding word line, a read/write circuit (61) for transferring the
voltage level of the sensing line to the corresponding word line for the column, data
output means (Q Y1 , 62) responsive to the voltage level on the data line for providing
a data output (D out ) corresponding to the stored data in the read cell, and data
refreshing means (59) for applying a write voltage(V W ) to the word line of the read
cell such that data corresponding to the voltage level on the data line is written back
into the previously read cell.
Claim 40
Dependent Claim
58 words
A memory device according to claim 39 including means (Q Y1 , 62) for
changing the level of voltage on the data line after operation of the read/write circuit
(61) in response to input data (D in ) to be written into the cell, whereby the write
voltage causes the input data to be written to the cell.
Claim 41
Dependent Claim
31 words
A memory device according to any one of claims 35 to 40 wherein the array
includes peripheral circuits (59-61) formed on a common substrate with the memory
cells (M mn ).
Claim 42
Dependent Claim
38 words
A memory device according to claim 41 wherein the peripheral circuits (59-61)
include transistors that include regions formed by the same process steps that are used
to form corresponding regions (5, 6) in the cells of the array.
Claim 43
Independent Claim
95 words
A method of fabricating a memory device which includes a path for charge
carriers, a node for storing charge that alters the conductivity of the path, and a
tunnel barrier configuration through which charge carriers tunnel in response to a
given voltage so as to become stored on the node, the method including forming the
tunnel barrier configuration such that it exhibits an energy band profile that
comprises a dimensionally relatively wide barrier component with a relatively low
barrier height, and at least one dimensionally relatively narrow barrier component
with a relatively high barrier height.
Claim 44
Dependent Claim
20 words
A method according to claim 43 including forming the tunnel barrier
configuration from regions of relatively conductive and insulating material.
Claim 45
Dependent Claim
13 words
A method according to claim 44 including forming said regions as overlying
layers.
Claim 46
Dependent Claim
18 words
A method according to claim 45 including forming an insulating layer with a
thickness of 3nm or less.
Claim 47
Dependent Claim
20 words
A method according to claim 45 or 46 including forming a conductive layer
with a thickness of 10nm or less.
Claim 48
Dependent Claim
30 words
A method according to claim 45, 46 or 47 including providing a layer of
silicon to form the conductive layer and treating the surface thereof to form the
insulating layer
Claim 49
Dependent Claim
19 words
A method according to claim 48 including nitriding the surface of the silicon
layer to form the insulating layer.
Claim 50
Independent Claim
21 words
A method according to any one of claims 43 to 49 including forming the node
as a layer of conductive material.
Claim 51
Independent Claim
22 words
A method according to any one of claims 43 to 49 including forming the node
as a of plurality of conductive islands.
Claim 52
Dependent Claim
14 words
A method according to claim 51 including distributing the islands in the
barrier configuration.
Claim 53
Dependent Claim
15 words
A method according to claim 51 or 52 including forming the islands of
semiconductor material.
Claim 54
Dependent Claim
14 words
A method according to claim 51 or 52 including forming the islands by
sputtering.
Claim 55
Dependent Claim
16 words
A method according to claim 51 or 52 including depositing the islands from a
liquid suspension.
Claim 56
Independent Claim
32 words
A method according to any one of claims 43 to 55 including forming a gate
electrode for applying an electric field to the tunnel barrier configuration to control
the barrier configuration thereof.
Claim 57
Independent Claim
21 words
A method according to any one of claims 43 to 56 including forming source
and drain regions coupled to the path.
Claim 58
Independent Claim
26 words
A method according to any one of claims 43 to 56 including forming a
plurality of the memory devices in an array in a common substrate.
Claim 59
Dependent Claim
24 words
A method according to claim 58 including forming peripheral circuits for
reading and writing data to and from the array in said common substrate.
Claim 60
Dependent Claim
17 words
A memory device fabricated by a method as claimed in any one of claims 43
to 59.
Claim 61
Dependent Claim
23 words
An array of memory devices formed on a common substrate by a method in
accordance with any one of claims 43 to 59.
References Cited (Backward Citations)
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