Method of manufacturing an electrically erasable and programmable non-volatile memory cells arrangement

Abstract

Abstract Production of an electrically writable and erasable read-only memory cell structure comprises etching parallel trenches (4) in an insulated first conductivity type doped region, formed in a semiconductor substrate (1) surface (3), and producing rows of memory cells, consisting of MOS transistors with second opposite conductivity type doped source/drain regions, a first dielectric (6), a floating gate (7"), a second dielectric (12) and a control gate (13), the rows being located alternately at the surface (3) between the trenches (4) and at the trench bottoms. The cells are produced by (a) forming a first dielectric layer (6) and a first doped polysilicon layer; (b) depositing and anisotropically etching (selectively wrt. the substrate) a first sacrificial layer on the polysilicon layer portions on the trench side walls in order to form spacers; (c) forming, on the exposed polysilicon layer portions, a second sacrificial layer which is selectively etchable wrt. the first sacrificial layer and the polysilicon layer; (d) removing the spacers selectively wrt. the second sacrificial layer; (e) etching the first polysilicon layer, using the second sacrificial layer as etching mask, to form a first polysilicon stripe structure arranged parallel to the trenches at the surface (3) between the trenches (4) and at the trench bottoms, the structure width at the trench bottoms being less than the trench width so that the sides of the structure are exposed; (f) removing the second sacrificial layer; (g) forming insulation structures (11), of height less than the polysilicon structure height, between the trench walls and the polysilicon structure at the trench bottoms; (h) forming a second dielectric layer (12); (i) depositing and structuring a second polysilicon layer to form control gates (13), which also cover the sides of the first polysilicon structures in the trenches (4), and to form word lines (13) which extend transversely to the rows and which are connected with the control gates of MOS transistors of different rows; (j) structuring the second dielectric layer (12) and the first polysilicon structure by anisotropic etching corresponding to the word lines to form the floating gates (7"); and (k) carrying out source/drain implantation using the word lines (13) as mask.

Inventors

• 👤 Wolfgang Dr. Krautschneider
• 👤 Franz Dr. Hofmann
• 👤 Hans Dr. Reisinger
• 👤 Josef Dr. Willer

Bibliographic Details