Semiconductor integrated circuit device with elements isolated by trenches

Claim 2

A semiconductor integrated circuit device comprising a semiconductor substrate (31, 32); a plurality of trenches (33A, 33B, 33C, ...) formed in parallel at the surface of said semiconductor substrate; active regions (35a1, 35a2, ..., 35b1, 35b2, ..., 35c1, 35c2, ..., 35d1, 35d2, ..., 35e1, 35e2, ..., 35f1, 35f2, ...) formed separately from each other at the bottom of each of said trenches (33A, 33B, 33C, ...) and in the semiconductor substrate (31, 32) of each projecting portion between said trenches; a plurality of floating gates (38a, 38b, 38c, 38d, ...) each provided above and between said active regions at the bottom of each of said trenches and above and between said active regions at each projecting portion between said trenches; and a control gate (40) extended over said plurality of floating gates in the direction that crosses said trenches, characterized in that the cell transistors formed at the bottom of each of said trenches are electrically isolated from the cell transistors formed on each projecting portion between said trenches by separating the former from the latter in the direction of depth of said trenches.

Claim 3

A semiconductor integrated circuit device comprising a semiconductor substrate (31) of a first conductivity type; a well region of a second conductivity type formed in the main surface region of said semiconductor substrate; a plurality of trenches (33A, 33B, 33C, ..) formed in parallel in said well region; drain and source regions (35a1, 35a2, ..., 35b1, 35b2, ..., 35c1, 35c2, ..., 35d1, 35d2, ..., 35e1, 35e2, ..., 35f1, 35f2, ...) of the first conductivity type formed separately from each other at the bottom of each of said trenches (33A, 33B, 33C, ...) and in said semiconductor substrate (31, 32) of each projecting portion between said trenches; first gate insulating films (37) which are each formed above and between said drain and source regions at the bottom of each of said trenches and above and between said drain and source regions on each projecting portion between said trenches, and through which tunnel current flows; a plurality of floating gates (38a, 38b, 38c, 38d, 38e, ...) each formed on said first gate insulating films; second gate insulating films (39a, 39b, 39c, 39d, 39e, ...) formed on the surface of said floating gates; and a plurality of control gates (41) formed in parallel on said second gate insulating films and extended over said plurality of floating gates in the direction perpendicular to said trenches, characterized in that the cell transistors (13-1 to 13-8) formed at the bottom of each of said trenches are electrically isolated from the cell transistors (13-1 to 13-8) formed on each projecting portion between said trenches by separating the former from the latter in the direction of depth of said trenches, and NAND type E² PROM cells where the current paths of a plurality of cell transistors are connected in series are formed at the bottom of each of said trenches and on each projecting portion between said trenches in the direction in which said trenches extend.

Claim 4

A semiconductor integrated circuit device comprising a semiconductor substrate (50) of a first conductivity type; a plurality of trenches (33A, 33B, 33C, ...) formed in parallel in a first direction at the surface of said semiconductor substrate; drain and source regions (35a1, 35a2, ..., 35b1, 35b2, ..., 35c1, 35c2, ..., 35d1, 35d2, ..., 35e1, 35e2, ..., 35f1, 35f2, ...) of a second conductivity type formed separately from each other at the bottom of each of said trenches and in said semiconductor substrate of each projecting portion between said trenches; first gate insulating films (37) which are each formed above and between said drain and source regions at the bottom of each of said trenches and above and between said drain and source regions on each projecting portion between said trenches; a plurality of floating gates (38a, 38b, 38c, 38d, 38e, ...) each formed on said first gate insulating films; second gate insulating films (39a, 39b, 39c, 39d, 39e, ...) formed on the surface of said floating gates; a plurality of control gates (41) formed in parallel on said second gate insulating films and extended over said plurality of floating gates in a second direction perpendicular to said first direction; an interlayer insulating film (52) formed on the resultant structure, with contact holes (53a1, 53a2, ..., 53b1, 53b2, ..., 53c1, 53c2, ..., 53d1, 53d2, ..., 53e1, 53e2, ..., 53f1, 53f2, ...) made in the positions on said interlayer insulating film above and corresponding to said drain and source regions; source lines (54) formed in said second direction on said interlayer insulating film and connected to said source regions via the contact holes made above said source regions; and bit lines (55a, 55b, 55c, 55d, 55e, 55f, ...) formed in said first direction on said interlayer insulating film and electrically isolated from said source lines and connected to said drain regions via the contact holes made above said drain regions, characterized in that the cell transistors formed at the bottom of each of said trenches are electrically isolated from the cell transistors formed on each projecting portion between said trenches by separating the former from the latter in the direction of depth of said trenches, and NOR type EE² PROM cells are formed at the bottom of each of said trenches and on each projecting portion between said trenches.

Claim 5

A semiconductor integrated circuit device according to claim 1 or 2, characterized in that said semiconductor substrate contains a semiconductor substrate (31) of a first conductivity type and a well region (32) of a second conductivity type formed in the surface region of the first-conductivity-type semiconductor substrate, and said trenches (33A, 33B, 33C, ...) are formed in said well region.

Claim 6

A semiconductor integrated circuit device according to claim 3 or 5, characterized by further comprising an inversion prevention impurity diffusion region (34) of the second conductivity type which is formed in said well region (32) and whose impurity concentration is higher than that of said well region.

Claim 7

A semiconductor integrated circuit device according to claim 4, characterized by further comprising an inversion prevention impurity diffusion region (34) of the first conductivity type which is formed in said semiconductor substrate (50) and whose impurity concentration is higher than that of said semiconductor substrate.

Claim 8

A semiconductor integrated circuit device according to claim 1, 2, 3 or 4, characterized by further comprising inversion prevention spacers (36a, 36b, 36c, 36d, ...) formed on the sidewall portions of said trenches (33A, 33B, 33C, ...).

Claim 9

A semiconductor integrated circuit device according to claim 8, said spacers are insulating layers (36a, 36b, 36c, 36d, ...) formed on said sidewall portions of said trenches (33A, 33B, 33C, ...).

Claim 10

A semiconductor integrated circuit device according to claim 3, characterized by further comprising an interlayer insulating film (41) formed on said control gate (40) and said semiconductor substrate (31, 32), and bit lines (11) formed in the same direction that said trenches extend on said interlayer insulating film (41) on the bottom of each of said trenches (33A, 33B, 33C, ...) and on each projecting portion between said trenches.

Claim 11

A semiconductor integrated circuit device according to claim 10, characterized by further comprising first and second cell select transistors (12-1, 12-2) for selecting said plurality of cell transistors (13-1 to 13-8) said current paths of which are connected in series, with said bit lines (11) connected to the drains (12-1D) of said first cell select transistors (12-1) and the sources (12-2S) of the second cell select transistors (12-2) grounded.

Claim 12

A semiconductor integrated circuit device according to claim 7, characterized by further comprising a low-concentration impurity diffusion region for alleviating electric fields which is inserted between said drain and source regions (35a1, 35a2, ..., 35b1, 35b2, ..., 35c1, 35c2, ..., 35d1, 35d2, ..., 35e1, 35e2, ..., 35f1, 35f2, ...) and said inversion prevention impurity diffusion region (34).