EP0786776A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semi-conductor integrated circuit device having an internal power supply circuit capable of stably maintaining output level against load fluctuation
Assignee: Mitsubishi Electric Corp
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Filing: 1996-07-05
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Granted: —
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Expires: 2016-07-05
Abstract
Abstract An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage (int. Vcc) while not increasing layout area. A differential amplifying circuit (202) in a voltage down converter (109) controls potential level V OUT of the drain of transistor P14 such that it attains the reference potential V REF . If the potential V OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V OUT is pulled down. By contrast, if the potential level V OUT lowers, transistor P12 is rendered conductive, and the potential level V OUT is pulled up.
Inventors
- 👤 Yutaka c/o Mitsubishi Denki K.K. Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 01:03
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C5/00; G11C5/14; G11C5/147; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
158 words
A semiconductor integrated circuit device, comprising: a first power supply node to which a first power supply potential (Vss) is supplied; a second power supply node to which a second power supply potential (ext. Vcc) is supplied; and an internal voltage supplying means (109), including voltage generating means (202, P14) for generating a prescribed internal voltage (int. Vcc) between said first and second power supply potentials, first and second capacitance means (C1, C2) each having one end connected to an output node of said voltage generating means, first voltage control means (N11, N12) responsive to lowering of a potential at the other end of said first capacitance means (C2) for rendering conductive connection between said first power supply node and said output node, and second voltage control means (P11, P12) responsive to increase in potential at the other end of said second capacitance means for rendering conductive connection between said second power supply node and said output node.
Claim 2
Dependent Claim
195 words
The semiconductor integrated circuit device according to claim 1, wherein said first voltage control means includes a first MOS transistor (N12) of a first conductivity type having source and drain connected to said first power supply node and to said output node, respectively, and a second MOS transistor (N11) of the first conductivity having source and drain connected to said first power supply node and to the other end of said first capacitance means, respectively, said first and second MOS transistors having their gates connected to each other and said second MOS transistor having its gate and drain connected to each other; and said second voltage control means includes a third MOS transistor (P12) of a second conductivity type having source and drain connected to said second power supply node and to said output node, respectively, and a fourth MOS transistor (P11) of the second conductivity type having source and drain connected to said second power supply node and to the other end of said second capacitance means, respectively, said third and fourth MOS transistors having their gates connected to each other and said fourth MOS transistor having gate and drain connected to each other.
Claim 3
Dependent Claim
79 words
The semiconductor integrated circuit device according to claim 2, wherein said first voltage control means includes a fifth MOS transistor (N13) of the first conductivity type connected parallel to said second MOS transistor and having its gate connected to said first power supply node; and said second voltage control means includes a sixth MOS transistor (P13) of the second conductivity type connected parallel to said fourth MOS transistor and having its gate connected to said second power supply node.
Claim 4
Dependent Claim
113 words
The semiconductor integrated circuit device according to one of claims 1 to 3, wherein said voltage generating means includes differential amplifying means (202) for generating an output potential in accordance with a difference between input potentials applied to first and second input nodes, and a seventh MOS transistor (P14) of the first conductivity type having its source connected to said first power supply node and receiving at its gate the output potential from said differential amplifying means, said first input node receiving a prescribed reference potential (V REF ), and the drain of said seventh MOS transistor and said second input node are connected to the output node of said voltage generating means.
Claim 5
Dependent Claim
214 words
The semiconductor integrated circuit device according to one of claims 1 to 4, wherein said voltage generating means includes an eighth MOS transistor (P31) of the second conductivity type connected between said first power supply node and said output node, a ninth MOS transistor (N31) of the first conductivity type connected between said second power supply node and said output node, and bias means controlling gate potential of said eighth and ninth MOS transistors; said bias means includes a first resistor (R3) having one end connected to said first power supply node, a tenth MOS transistor (P32) of the second conductivity type having its drain and gate connected to the other end of said first resistor, a second resistor (R4) connected between the source of said tenth MOS transistor and said second power supply node, a third resistor (R1) having one end connected to said second power supply node, an eleventh MOS transistor (N32) of the first conductivity type having its drain and gate connected to the other end of said third resistor, and a fourth resistor (R2) connected between the source of said eleventh MOS transistor and said first power supply node; and said eighth and ninth MOS transistors have their gates connected to the gates of said tenth and eleventh MOS transistors.
References Cited (Backward Citations)
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