Field programmable memory array

Claim 2

The programmable memory array of claim 1, further comprising a configuration memory connected to the configuration circuitry for holding user-selected access mode information.

Claim 3

The programmable memory array of claims 1 or 2, wherein each respective user-selected access mode can be selected from the group consisting of wide memory and deep memory.

Claim 4

The programmable memory array of claims 1 or 2, wherein each respective user-selected access mode can be selected from the group consisting of FIFO, wide memory and deep memory.

Claim 5

The programmable memory array of claims 1 or 2, wherein each respective user-selected access mode can be selected from the group consisting of single port memory and dual port memory.

Claim 6

The programmable memory array of claims 1 or 2, wherein each respective user-selected access mode can be selected from the group consisting of single port and dual port register arrays.

Claim 7

A programmable gate array having a plurality of programmable logic cells therein, the programmable gate array further comprising a programmable memory array as set forth in any one of the preceding claims.

Claim 8

The programmable memory array of any one of claims 1 to 6 wherein a respective user-selected access mode comprises a read-only memory.

Claim 9

A programmable memory array, comprising: at least one sub-array having a plurality of memory cells; a line for propagating memory cell data away from the cells of the at least one sub-array; a precharge device programmably connectable to the line; and a drive device connected between the cells of the at least one sub-array and the line, the drive device programmably operable in a first mode wherein discharge of the said line in accordance with the memory cell data is effected, and a second mode wherein drive of said line in accordance with the memory cell data is effected.

Claim 10

A programmable memory circuit comprising: a memory cell for holding data; a first word line that propagates a first select signal; a first bit line; a first selective coupler disposed between said first bit line and said memory cell, selectively coupling said first bit line and said memory cell in accordance with said first select signal for propagating a signal therebetween; an output interface connected to said memory cell for carrying a signal from said memory cell; and an additional data line connected to said memory cell for carrying a signal to said memory cell.

Claim 11

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines.

Claim 12

A programmable memory circuit comprising an array of bit/word line addressable memory cells including: a first memory cell addressable per a first word line for enabling primary data access thereto; a second memory cell addressable per a second word line, for enabling primary data access thereto; a transfer cell disposed intermediate said first memory cell and said second memory cell for providing intermediate data storage; a first selective coupler enabled per a first clock for selectively coupling said transfer cell and said first memory cell, enabling data propagation therebetween; and a second selective coupler enabled per a second clock for selectively coupling said transfer cell and said second memory cell, enabling data propagation therebetween; whereby said first and second clocks are operated sequentially for transferring data from one of said first and second memory cells to the other.

Claim 14

A memory array comprising a plurality of memory cells arranged in rows and columns, each row of memory cells having associated therewith an addressable enable word line, and each column of memory cells having associated therewith a bit line, each bit line providing access to memory cells of said associated column as enabled via respective addressable enable word lines, said memory array further comprising: a plurality of discrete couplers, each discrete coupler of the plurality of discrete couplers being disposed between respective adjacent memory cells of a given column; each discrete coupler being operative for selectively shifting data within the given column from one of the respective adjacent memory cells to the other in accordance with a push/pop control signal.

Claim 15

A memory array comprising a plurality of memory cells arranged in rows and columns, each row of cells having associated therewith a word line selectively addressable by an associated row address, and each column of cells having associated therewith a bit line that provides access to memory cells of said associated column as enabled via respective word lines, said memory array further comprising: an address decoder having an address input for receiving an input address, said address decoder selecting said word lines in accordance with said input address; and a programmable access unit for providing read and write input addresses to the address input of said address decoder during associated read and write operations of said memory array, said programmable access unit modifying said read and write addresses during operations of said memory array so as to provide one of Last In First Out (LIFO), or First In First Out (FIFO), memory functionality in accordance with a mode select signal.

Claim 16

A programmable memory array having a plurality of memory cells arranged in rows and columns, a row of cells having an associated word line, and a column of cells having associated therewith a programmable bit line structure, said programmable bit line structure of the column of cells comprising: a plurality of local bit lines, each local bit line of said plurality of local lines being associated with a respective sub-array group of memory cells of said given column of cells; and a local selective coupler between adjacent local bit lines of said plurality of local bit lines, said selective coupler being programmable for selectively propagating a signal therebetween.

Claim 17

A programmable intercoupling circuit of a programmable memory array having a primary I/O bus and a secondary I/O bus, said programmable intercoupling circuit comprising: a first selective coupler having an output and a plurality of inputs, inputs of said plurality of inputs being coupled to select primary interconnects of said primary I/O bus interconnects, said first selective coupler being programmable for selectively propagating a signal between said output and one input of said plurality of inputs in accordance with a first select signal; and a second selective coupler having an input electrically coupled for receiving a signal associated with the output of said first selective coupler, and a plurality of outputs, outputs of said plurality of outputs being coupled to select secondary interconnects of said secondary I/O bus, said second selective coupler being programmable for selectively propagating a signal between said input and one output of said plurality of outputs in accordance with a second select signal.

Claim 18

A programmable intercoupling circuit of a programmable memory array having a primary I/O bus and a secondary I/O bus, said programmable intercoupling circuit comprising: a programmable read port having means for selectively propagating, in accordance with a first select signal, a first signal from a select secondary interconnect of said secondary I/O bus to a select primary interconnect of said primary I/O bus; and a programmable write port having means for selectively propagating, in accordance with a second select signal, a second signal from a select primary interconnect of said primary I/O bus to a select secondary interconnect of said secondary I/O bus.

Claim 19

A programmable address decoder comprising: M word lines; a plurality of address lines for propagating address data; a programmable inverter disposed in series with a given address line of said plurality of address lines, said programmable inverter selectively inverting a signal propagating along said given address line in accordance with an address polarity select signal; and a decoder circuit selectively driving a given word line of said M word lines as selected in accordance with address data of said plurality of address lines as processed per said programmable inverter.

Claim 20

A programmable address decoder comprising: M word lines; a plurality of address lines for propagating address data; a decoder circuit selectively driving a given word line of said M word lines as selected in accordance with address data of said plurality of address lines; and a selective coupler having a plurality of inputs coupled to an associated set of lines of an address bus, and an output coupled to an address line of said plurality of address lines, said selective coupler selectively coupling its output to one of its plurality of inputs in accordance with associated configuration data.

Claim 21

A programmable address decoder comprising: M word lines; a plurality of address inputs for receiving address data; an enable input for receiving an enable signal; logic means for selectively driving one word line of said M word lines when its associated address data is received at said plurality of address inputs and when enabled per said enable signal; and programmable means for providing said enable signal in accordance with an enable select signal.

Claim 22

A memory array having: a plurality of memory cells arranged in rows and columns, said rows of memory cells being selectable per respective word lines for loading data therein, said plurality of memory cells sharing a common reset signal; and a programmable address decoder having M word line outputs coupled to the respective word lines of said plurality of rows of memory cells, a plurality of inputs for receiving address data for addressing select word line outputs in accordance with said address data, and a reset disable input for receiving said common reset signal, said programmable address decoder disabling said M word line outputs in accordance with said common reset signal.

Claim 23

A programmable memory array comprising: a plurality of memory sub-arrays, each memory sub-array including a plurality of memory cells arranged in rows and columns, a plurality of local bit lines wherein each column of memory cells has an associated local bit line of said plurality of local bit lines for presenting/receiving data to/from the memory cells thereof, and a plurality of word lines wherein each row of said plurality of memory cells has an associated word line providing a select signal for controlling access of the memory cells of said row to associated local bit lines; and a programmable bus matrix for selectively configuring local bit lines of the various memory sub-arrays; said programmable bus matrix being programmable in a first configuration wherein the local bit lines of one sub-array of said plurality of sub-arrays are electrically intercoupled to corresponding local bit lines of another sub-array of said plurality of sub-arrays so as to provide common bit lines for the respective memory cells of the corresponding columns of said one and said another sub-arrays; and said programmable bus matrix being programmable in a second configuration wherein the local bit lines of said one sub-array of said plurality of sub-arrays are electrically configured in parallel with corresponding local bit lines of said another sub-array of said plurality of sub-arrays so as to provide separate, parallel bit lines for accessing the memory cells of the corresponding columns of said one and said another sub-arrays.

Claim 24

A memory array comprising: Z memory blocks, each of said memory blocks comprising a generally rectangular sub-array of M x N memory cells; address lines connectable to each of said memory blocks; data lines connectable to each of said memory blocks; I/O circuitry; and programming elements distributed within said address lines, data lines, and I/O circuitry such that at least one portion of said Z memory blocks can be configured into an iM x jN memory, wherein i and j are positive integers, by programming said programming elements.

Claim 25

A bit line hierarchy structure for a plurality of memory units, comprising: a plurality of first hierarchy bit lines, each first hierarchy bit line being associated with a given memory unit of the plurality of memory units; a plurality of second hierarchy bit lines, each second hierarchy bit line being associated with a different respective grouping of memory units of the plurality of memory units, each second hierarchy bit line partially overlapping at least one other second hierarchy bit line wherein the respective groupings of memory units of said each second hierarchy bit line and said one other second hierarchy bit line share a common memory unit; and selective multiplexer means provided with each memory unit for selectively coupling said each memory unit to one of its associated first and second hierarchy bit lines.

Claim 26

A selective read capture latch for selectively interfacing a hierarchal bit line structure, said selective read capture latch comprising: at least first and second hierarchy inputs for receiving data from respective first and second hierarchy bit lines of the hierarchical bit line structure; a memory unit having an input and output, said memory unit for retaining data per data received at its input, and providing output data at its output per data retained therein; and selective coupling means between said at least first and second hierarchy inputs and said input of said memory unit, for selectively coupling one of said first and second hierarchy inputs to said input of said memory unit for propagating data therebetween in accordance with an associated hierarchy read capture clock.

Claim 27

A programmable memory array having a plurality of memory cells arranged in rows and columns, each row of cells having an associated addressable word line, and each column of cells having associated therewith a programmable bit line structure, said programmable bit line structure comprising: a plurality of first hierarchy bit lines, each of at least two first hierarchy bit lines of said plurality of first hierarchy bit lines being associated with a respective sub-array group of memory cells of said given column of cells; a second hierarchy bit line associated with a respective segment of memory cells of said given column, said segment encompassing said sub-array groups of memory cells of said given column as associated with said at least two first hierarchy bit lines; an internal sub-array bit line associated with each sub-array group of memory cells, said internal sub-array bit lines providing propagation of data as read from a given memory cell of its associated sub-array group in said given column as addressably enabled per its associated row word line; a selective coupler for at least one of said programmable internal sub-array bit lines, in accordance with given hierarchical configuration data for selectively propagating a signal between its associated internal sub-array bit line and one bit line of the group including at least one of said first hierarchy bit lines said second hierarchy bit lines; a read port for outputting data as read from the given memory cell of said given column of memory cells; and a selective read capture latch for selectively capturing data therein from a select bit line of at least one of said first hierarchy bit lines and said second hierarchy bit line, and having an output for providing said captured data to said read port.