Patent EP0772200A1 successfully refreshed from Google Patents.
EP0772200A1
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Voltage generator for electrically programmable non-volatile memory cells
Assignee: STMicroelectronics SRL
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Filing: 1995-10-31
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Granted: —
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Expires: 2015-10-31
Abstract
Abstract The present invention relates to a voltage (hv) generator (4) for electrically programmable non-volatile memory cells (2), being of a type which comprises a plurality of charge pump circuits (11A,11B) having inputs controlled by a plurality of phase generators (9) and outputs connected to an output terminal (OUT) of the voltage generator (4), the charge pump circuits (11A,11B) being laid as pairs (11) of first (11A) and second (11B) charge pump circuits, and the first charge pump circuits (11A) being active when the second charge pump circuits (11B) are inactive, and vice versa. The invention also concerns a charge pump circuit, a phase generator (9) and a clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2).
Inventors
- 👤 Fabio Tassan Caser
- 👤 Marco Dellabora
- 👤 Marco Defendi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:38
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/30; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
87 words
A voltage (hv) generator (4) for electrically programmable non-volatile memory cells (2), comprising a plurality of charge pump circuits (11A,11B) having their inputs controlled by a plurality of phase generators (9) and their outputs connected to an output terminal (OUT) of the voltage generator (4), characterized in that said charge pump circuits (11A,11B) are laid as pairs (11) of first (11A) and second (11B) charge pump circuits, the first charge pump circuits (11A) being active while the second charge pump circuits (11B) are inactive, and vice versa.
Claim 2
Dependent Claim
66 words
A voltage (hv) generator (4) according to Claim 1, characterized in that each of said phase generators (9), connected to said charge pump circuits (11A,11B)) through a bus (10), supplies a plurality of phase signals (A,B,C,D), having the same frequency (f) and being shifted in phase from each another by a suitable amount, for controlling in opposition phase the pairs (11) of charge pump circuits (11A,11B).
Claim 3
Dependent Claim
54 words
A voltage (hv) generator (4) according to Claim 2, characterized in that said phase generators (9) are connected to a clock generator circuit (7) being input a control signal (PROG) and outputting a plurality of clock signals (ck〈1〉,ck〈2〉,ck〈3〉,ck〈4〉) with the same frequency (f) and shifted in phase from each other by a suitable amount.
Claim 4
Dependent Claim
66 words
A voltage (hv) generator (4) according to Claim 1, characterized in that it includes a voltage limiter circuit (13) having an input connected to the output terminal (OUT) of the voltage generator (4) and an output connected to the charge pump circuits (11A,11B), said voltage limiter circuit (13) being input a control signal (PROG) and a programming voltage signal (Vpd) for programming the memory cells (2).
Claim 5
Dependent Claim
87 words
A voltage (hv) generator (4) according to Claim 1, characterized in that it comprises at least four pairs (11) of charge pump circuits (11A,11B) connected to respective phase generators (9), each first charge pump circuit (11A) being input first (A), second (B) and third (C) phase signals, each second charge pump circuit (11B) being input a fourth phase signal (D) and said first (A) and third (C) phase signals, said phase signals (A,B,C,D) being shifted in phase from each other by one eighth of a period (1/f).
Claim 6
Dependent Claim
62 words
A voltage (hv) generator (4) according to Claim 1, characterized in that each of said charge pump circuits (11A,11B) includes at least first (IA), second (IB) and third (IC) input terminals receiving respective phase signals (A,B,C) from one of the phase generators (9), said circuits being connected to an output terminal (OP) through first (Cp1), second (Cp2) and third (Cp3) pump capacitors.
Claim 7
Dependent Claim
100 words
A voltage (hv) generator (4) according to Claim 6, characterized in that said first input terminal (IA) is connected to said first pump capacitor (Cp1) through an enabling circuit (44) comprising first (N8) and second (N9) transistors connected, in parallel with each other, between the first pump capacitor (Cp1), the first input terminal (IA) and a ground voltage reference (GND) of the charge pump circuit, the control terminals of said transistors (N8,N9) including first (TA1) and second (TA2) enabling terminals of the enabling circuit (44) respectively receiving first (STPAN) and second (STPA) enabling signals which are complementary of each other.
Claim 8
Dependent Claim
47 words
A voltage (hv) generator (4) according to Claim 6, characterized in that said second (Cp2) and third (Cp3) pump capacitors are connected to the output terminal (OP) of the charge pump circuit through a decoupling circuit (46) comprising first (N16), second (N17) and third (N18) MOS transistors.
Claim 9
Dependent Claim
137 words
A voltage (hv) generator (4) according to Claim 3, characterized in that said clock generator circuit (7) comprises a loop (14) of a plurality of primary inverters (15) and secondary inverters (16) which supply, on a plurality of outputs (O7), said clock signals (ck〈1〉,ck〈2〉,ck〈3〉,ck〈4〉), each of said primary inverters (15) having an input terminal (I15) connected to an output terminal (O16) of a secondary inverter (16) preceding it in the loop (14) and to the ground voltage reference (GND), through a MOS transistor (N1) controlled by a secondary control signal (PROGN) which corresponds to the negated control signal (PROG), in parallel with a capacitor (C), and having an output terminal (O15) connected to a first input (A) of the secondary inverter (16) lying next to it in the loop (14), and to one of the outputs (O7).
Claim 10
Dependent Claim
31 words
A voltage (hv) generator (4) according to Claim 1, characterized in that said first (Cp1), second (Cp2) and third (Cp3) pump capacitors comprise three-terminal capacitors in a parallel type of connection.
Claim 11
Dependent Claim
76 words
A charge pump circuit for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2), being of a type which comprises at least first (IA), second (IB) and third (IC) input terminals receiving respective phase signals (A,B,C) from a phase generator (9), characterized in that said input terminals (IA,IB,IC) are connected to an output terminal (OP) of the charge pump circuit through first (Cp1), second (Cp2) and third (Cp3) pump capacitors, respectively.
Claim 12
Dependent Claim
98 words
A charge pump circuit according to Claim 11, characterized in that said first input terminal (IA) is connected to said first pump capacitor (Cp1) through an enabling circuit (44) which comprises first (N8) and second (N9) MOS transistors connected, in parallel with each other, between the first pump capacitor (Cp1) and respectively the first input terminal (IA) and a ground voltage reference (GND), the control terminals of said transistors (N8,N9) including first (TA1) and second (TA2) enabling terminals of the enabling circuit (44) and receiving first (STPAN) and second (STPA) enabling signals which are complementary of each other.
Claim 13
Dependent Claim
158 words
A charge pump circuit according to Claim 11, characterized in that said second (Cp2) and third (Cp3) pump capacitors are connected to the output terminal (OP) through a decoupling circuit (46) comprising first (N16), second (N17) and third (N18) MOS transistors, the first transistor (N16) having its control (G16) and drain (D16) terminals connected together and to the source terminal (S17) of the second transistor (N17), as well as to the source terminal (S18) of the third transistor (N18) and to the second pump capacitor (Cp2), and having its source terminal (S16) connected to the drain terminal (D17) of the second transistor (N17) and to the control terminal (G18) of the third transistor (N18), as well as to the third pump capacitor (Cp3), and the second transistor (N17) also having its control terminal (G17) connected to the drain terminal (D18) of the third transistor (N18), in turn connected to the output terminal (OP) of the charge pump circuit.
Claim 14
Dependent Claim
93 words
A phase generator (9) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2), being of the type which comprises an input terminal (I9) and first (OA), second (OB), third (OC) and fourth (OD) output terminals, characterized in that said input terminal (I9) is connected to said output terminals (OA,OB,OC,OD) respectively through a series of first (25) and second (26) input logic inverters and respectively first (27), second (28), third (29) and fourth (30) circuit legs outputting first (GATE-A), second (GATE-B), third (GATE-C) and fourth (GATE-D) feedback signals.
Claim 15
Dependent Claim
42 words
A phase generator (9) according to Claim 14, characterized in that it further comprises first (21), second (22), third (23) and fourth (24) output logic inverters connected between said circuit legs (27,28,29,30) and respective output terminals (OA,OB,OC,OD) of the phase generator (9).
Claim 16
Dependent Claim
85 words
A phase generator according to Claim 14, characterized in that said first feedback signal (GATE-A) supplies the second circuit leg (28), said second feedback signal (GATE-B) supplies, through a first feedback logic inverter (37), the first circuit leg (27), and, through a second feedback logic inverter (38), the fourth circuit leg (30), said third feedback signal (GATE-C) supplies, through a third feedback logic inverter (40), the fourth circuit leg (30), and said fourth feedback signal (GATE-D) supplies the second (28) and third (29) circuit legs.
Claim 17
Dependent Claim
143 words
A clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2), characterized in that it comprises a loop (14) of a plurality of primary inverters (15) and secondary inverters (16) supplying clock signals (ck〈1〉,ck〈2〉,ck〈3〉,ck〈4〉) on a plurality of outputs (O7), each of said primary inverters (15) having an input terminal (I15) connected to an output terminal (O16) of a secondary inverter (16) preceding it in the loop (14), and to the ground voltage reference (GND) through a MOS transistor (N1) controlled by a secondary control signal (PROGN) which corresponds to the negated control signal (PROG), in parallel with a capacitor (C), and having an output terminal (O15) connected to a first input (A) of the secondary inverter (16) lying next to it in the loop (14), and to one of the output terminals (O7).
Claim 18
Dependent Claim
101 words
A clock generator circuit (7) according to Claim 17, characterized in that said loop (14) further comprises a logic gate (17) of the NAND type having a first input connected to the output terminal (O15) of one of the primary inverters (15) and an output connected to said first input (A) of one of the secondary inverters (16), said logic gate (17) being input the control signal (PROG), each of said secondary inverters (16) having second and third input terminals (PG,NG) which receive a pair of reference signals (IGAP/IGAN) being generated by a reference circuit (18) and complementary of each other.
Claim 19
Dependent Claim
121 words
A three-terminal capacitor adapted to be integrated monolithically to a semiconductor structure (49), comprising a semiconductor substrate (50) with a first dopant type (P) accommodating an epitaxial well (51) with a second dopant type (N) on whose inside a first diffused region (52) is provided which has a higher concentration of the second dopant type (N+), said epitaxial well (51) being covered by a layer (53) of gate oxide, a first layer (POLY1) of polycrystalline silicon and a further layer (54) of interpoly oxide, and a second layer (POLY2) of polycrystalline silicon, characterized in that said second layer (POLY2) of polycrystalline silicon comprises a first portion (POLY2A) and second portion (POLY2B) which are structurally independent and separated one from the other.
Claim 20
Dependent Claim
42 words
A three-terminal capacitor adapted to be integrated monolithically according to Claim 19, characterized in that said first layer (POLY1) of polycrystalline silicon and said first portion (POLY2B) of said second layer (POLY2) of polycrystalline silicon are directly in contact with each other.
Claim 21
Dependent Claim
65 words
A three-terminal capacitor adapted to be integrated monolithically according to Claim 20, characterized in that said first portion (POLY2A) of the second layer (POLY2) of polycrystalline silicon includes a first capacitor contact terminal (TC1), said second portion (POLY2B) of the second layer (POLY2) of polycrystalline silicon includes a second capacitor contact terminal (TC2), and said diffused region (52) includes a third capacitor contact terminal (TC3).
Claim 22
Dependent Claim
30 words
A charge pump circuit according to Claim 11, characterized in that said first (Cp1), second (Cp2) and third (Cp3) pump capacitors are three-terminal capacitors in a parallel type of connection.
Claim 23
Dependent Claim
29 words
A programming circuit for a matrix array of electrically programmable non-volatile memory cells (2), characterized in that it includes at least one voltage regulator as claimed in Claim 1.
Claim 24
Dependent Claim
30 words
A programming circuit for a matrix array of electrically programmable non-volatile memory cells (2), characterized in that it includes at least one charge pump circuit as claimed in Claim 11.
Claim 25
Dependent Claim
29 words
A programming circuit for a matrix array of electrically programmable non-volatile memory cells (2), characterized in that it includes at least one phase generator as claimed in Claim 14.
Claim 26
Dependent Claim
30 words
A programming circuit for a matrix array of electrically programmable non-volatile memory cells (2), characterized in that it includes at least one clock generator circuit as claimed in Claim 17.
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