Patent EP0709769A2 successfully refreshed from Google Patents.
EP0709769A2
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Apparatus and method for the analysis and resolution of operand dependencies
Assignee: International Business Machines Corp
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Filing: 1995-09-22
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Granted: —
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Expires: 2015-09-22
Abstract
Abstract An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.
Inventors
- 👤 James Henry Hesson
- 👤 Jay Leblanc
- 👤 Stephen J. Ciavaglia
- 👤 Walter Thomas Esling
- 👤 Pamela Anne Wilcox
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 02:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3824; G06F9/3834; G06F9/3838; G06F9/384; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
193 words
A pipelined microprocessor capable of issuing and executing instructions out-of-order in a single processor cycle comprising: an instruction cache for temporarily storing instructions to be executed and a data cache for temporarily storing program data; an instruction fetch and dispatch unit receiving instructions from said instruction cache; a plurality of execution units receiving operands from said data cache and operating on said operands according to instructions issued to the execution units, a register file, a completion buffer and a writeback unit, the completion buffer receiving operand results from the execution units and supplying the register file with operand results during a last stage of a pipeline stage, and the writeback unit receiving operand results from the completion buffer for writing data to memory; and a rename unit controlling dispatch of instructions from the instruction fetch and dispatch unit, issuing instructions to the execution units, and writeback of instructions from the completion buffer, said rename unit performing source operand dependency analysis, providing instruction scheduling wherein oldest instructions are executed first, enabling any execution or memory access instruction to execute out-of-order, and rapid pipeline recovery due to a mispredicted branch or a store load conflict.
Claim 2
Dependent Claim
86 words
The pipelined microprocessor according to claim 1 wherein said rename unit comprises: a rotating stack which maintains a record of program order; means for allocating rename tags from a list of rename tags in circular order and storing the rename tags in the rotating stack; and priority encode and state transition logic responsive to said rotating stack for performing instruction dispatch operations, instruction issue operations, instruction writeback operations and rapid pipeline recovery, pipeline recovery being performed by a partial flush of contents of the rename unit.
Claim 3
Dependent Claim
104 words
The pipelined microprocessor according to claim 2 further comprising: a branch target cache loaded from the completion buffer and controlled by the instruction fetch and dispatch unit with a branch target address; and a store barrier cache accessed by the instruction fetch and dispatch unit in parallel with the instruction cache, the store barrier cache containing history bits from the completion buffer that are used to predict a store load conflict, the rename unit marking a store instruction during a dispatch pipeline stage so that no loads in program order are permitted to execute ahead of the store that is predicted to be violated.
Claim 4
Dependent Claim
67 words
The pipelined microprocessor according to claim 2 or 3 further comprising a central pool of reservation station buffers, the rename unit during a dispatch pipeline stage dispatching instructions to the central pool of reservation station buffers and during an execution dispatch pipeline stage directing said execution units to perform an oldest instruction that has each of its operands valid from the central pool of reservation station buffers.
Claim 5
Dependent Claim
39 words
The pipelined microprocessor according to claim 4 wherein said execution units include fixed point units, a floating point unit, a branch unit, and a load/store unit, and wherein said register file is partitioned into integer and floating point files.
Claim 6
Independent Claim
112 words
A method of performing register renaming and rapid pipeline recover in a pipelined microprocessor capable of issuing and executing instructions out-of-order in a single processor cycle comprising the steps of: temporarily storing program data and instructions to be executed; performing source operand dependency analysis; providing instruction scheduling wherein oldest instructions are executed first by a plurality of execution units; dispatching instructions to a plurality of execution units and supplying the execution units with operands from the stored program data; enabling any execution or memory access instruction to execute out-of-order; temporarily storing operand results from the execution units; and providing rapid pipeline recovery due to a mispredicted branch or a store load conflict.
References Cited (Backward Citations)
US4574349A
Cited
US4992938A
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