Series parallel converter including pseudorandom noise generation

Claim 2

A circuitry with a pseudorandom noise generative function (1) as claimed in claim 1, characterized in that said exclusive OR gate (13) has two inputs being electrically connected to said shift register (11) for receipt of a most significant bit and a second bit from said most significant bit of said shift register (11) respectively.

Claim 3

A circuitry with a pseudorandom noise generative function (1) as claimed in claim 1, characterized in that said shift register (11) shifts said serial data synchronizing with a bit clock showing a respective position of bits of a word in said serial data and said shift register (11) converts said serial data into said parallel data synchronizing with word clocks showing ends of every words in said serial data.

Claim 4

A circuitry with a pseudorandom noise generative function (1) as claimed in claim 1, characterized in that said switch (14, 15) comprises a first switch (14) being electrically connected to an input of said shift register (11), said output of said exclusive OR gate (13) and said data line (112) of said serial digital data for selecting said serial digital data or said exclusive ORed data in response to said selective signal to supply it as said serial data to said shift register (11) and a second switch (15) being electrically connected to a data line (111) of said bit clock, a data line (110) of said word clock and clock inputs of said shift register (11) for selecting said bit clock or said word clock to supply it to said clock inputs in response to said selective signal.

Claim 5

A circuitry with a pseudorandom noise generative function (1) as claimed in claim 4, characterized in that said first switch (14) selects said digital data when receipt of said selective signal ordering said normal processing mode, while said first switch (14) selects said exclusive ORed data when receipt of said selective signal ordering said pseudorandom noise generative mode.

Claim 6

A circuitry with a pseudorandom noise generative function as claimed in claim 4, characterized in that said second switch (15) selects said bit clock when receipt of said selective signal ordering said normal processing mode, while said second switch (15) selects said word clock when receipt of said selective signal ordering said pseudorandom noise generative mode.

Claim 7

A circuitry with a pseudorandom noise generative function as claimed in claim 4, characterized in that said first and second switches (14, 15) comprises multiplexers.

Claim 8

A digital signal processing circuit comprising a first shift register (11) for converting serial data into parallel data, an arithmetic circuit (3) being electrically connected to said shift register (11) for fetching said parallel data from said shift register (11) and performing arithmetic on said parallel data and a second shift register (21) being electrically connected to said arithmetic circuit (3) for fetching said parallel data from said arithmetic circuit (3) and for converting said parallel data into serial data as output data, characterized by an exclusive OR gate (13) being electrically connected to said first shift register (11) for fetching outputs from said shift register (11), said exclusive OR gate (13) supplying exclusive ORed data to said first shift register (11) for use of generating a pseudorandom noise and a switch (14, 15) being electrically connected to a data line (112) transmitting serial digital data to be processed therein and an output of said exclusive OR gate (13) for fetching said digital data and said exclusive ORed data respectively to select said serial digital data or said exclusive ORed data in response to a selective signal, said switch (14, 15) being electrically connected to said first shift register (11) for supplying said serial digital data or said exclusive ORed data to said first shift register (11), thereby selecting a normal processing mode for said digital data or a pseudorandom noise generative mode for said exclusive ORed data;

Claim 9

A digital signal processing circuit as claimed in claim 8, characterized in that said exclusive OR gate (13) has two inputs being electrically connected to said shift register (11) for receipt of a most significant bit and a second bit from said most significant bit of said shift register (11) respectively.

Claim 10

A digital signal processing circuit as claimed in claim 8, characterized in that said shift register (11) shifts said serial data synchronizing with a bit clock showing a respective position of bits of a word in said serial data and said shift register (11) converts said serial data into said parallel data synchronizing with word clocks showing ends of every words in said serial data.

Claim 11

A digital signal processing circuit as claimed in claim 8, characterized in that said switch (14, 15) comprises a first switch (14) being electrically connected to an input of said shift register (11), said output of said exclusive OR gate (13) and said data line (112) of said serial digital data for selecting said serial digital data or said exclusive ORed data in response to said selective signal and a second switch (15) being electrically connected to a data line (111) of said bit clock, a data line (110) of said word clock for selecting and clock inputs of said shift register (11) for selecting said bit clock or said word clock to supply it to said clock inputs in response to said selective signal.

Claim 12

A digital signal processing circuit as claimed in claim 11, characterized in that said first switch (14) selects said digital data when receipt of said selective signal ordering said normal processing mode, while said first switch (14) selects said exclusive ORed data when receipt of said selective signal ordering said pseudorandom noise generative mode.

Claim 13

A digital signal processing circuit as claimed in claim 11, characterized in that said second switch (15) selects said bit clock when receipt of said selective signal ordering said normal processing mode, while said second switch (15) selects said word clock when receipt of said selective signal ordering said pseudorandom noise generative mode.

Claim 14

A digital signal processing circuit as claimed in claim 11, characterized in that said first and second switches comprises multiplexers.

Claim 15

A digital signal processing circuit comprising a first data line for transmitting serial digital data to be processed thereto, a second data line for transmitting a bit clock showing a respective position of bits of a word in said serial data thereto, a third data line for transmitting word clocks showing ends of every words in said serial data, a forth data line for transmitting a selective signal for selecting a normal processing mode or a pseudorandom noise generative mode, a first shift register for converting serial data into parallel data, said first shift register shifting said serial data into the next bit synchronizing with said bit clock and converting said serial data into said parallel data synchronizing with a word clock, an arithmetic circuit being electrically connected to said shift register for fetching said parallel data from said shift register and performing arithmetic on said parallel data and a second shift register being electrically connected to said arithmetic circuit for fetching said parallel data from said arithmetic circuit, said second n-bits shift register converting said parallel data into serial data synchronizing with said word clock and shifting said serial data into next bit respectively synchronizing with said bit clock, characterized by an exclusive OR gate being electrically connected to predetermined bits of said shift register for fetching outputs from said predetermined bits, said exclusive OR gate supplying exclusive ORed data to said shift register for generating a pseudorandom noise, a first multiplexer being electrically connected to said first data line and an output of said exclusive OR gate for fetching said serial digital data and said exclusive ORed data respectively, said first multiplexer being electrically connected to an input of said shift register and said fourth data line for selecting said serial digital data or said exclusive ORed data to supply it to said shift register in response to a selective signal and a second multiplexer being electrically connected to said second and third data lines for fetching said bit clock and said word clock respectively, said second multiplexer being electrically connected to clock inputs of said shift register and said fourth data line for selecting said bit clock or said word clock to supply it to clock inputs of said shift register in response to a selective signal, wherein said first switch selects said digital data when receipt of said selective signal ordering said normal processing mode, while said first switch selects said exclusive ORed data when receipt of said selective signal ordering said pseudorandom noise generative mode and wherein said second switch selects said bit clock when receipt of said selective signal ordering said normal processing mode, while said second switch selects said word clock when receipt of said selective signal ordering said pseudorandom noise generative mode.