EP0196152A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Testing digital integrated circuits
Assignee: Fujitsu Services Ltd
•
Filing: 1986-01-29
•
Granted: —
•
Expires: 2006-01-29
Abstract
Abstract A digital integrated circuit includes a register (10) having a normal mode of operation in which it acts as a parallel input/output register. The register also has a second mode of operation in which it acts as a pseudo-random number generator, and a third mode in which it is connected as a circular shift register. This allows the register to be used for producing a variety of different test sequences for testing other parts of the circuits e.g. for testing a programmable logic array included in the circuit.
Inventors
- 👤 Stuart George Hale
- 👤 Finbar Naven
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 19:11
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/31813; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G01R31/318516; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
74 words
A digital integrated circuit including at least one register (10) which is operable in a first mode in which it acts as a parallel input/output register, and in a second mode in which it acts as a pseudo-random number generator for producing test patterns for the circuit, characterised in that the register is also operable in a third mode in which it acts as a circular shift register for producing circularly shifting test patterns.
Claim 2
Dependent Claim
74 words
A digital integrated circuit including at least one register (10) which is operable in a first mode in which it acts as a parallel input/output register, and in a second mode in which it acts as a pseudo-random number generator for producing test patterns for the circuit, characterised in that the register is also operable in a third mode in which it acts as a circular shift register for producing circularly shifting test patterns.
Claim 3
Dependent Claim
19 words
A circuit according to claim 1 including a programmable logic array having said register (10) as an input register.
Claim 4
Dependent Claim
35 words
A circuit according to claim 1 or 2 wherein said register is one of a plurality of registers (A-D) each of which is operable in any one of the three modes specified in claim 1.
Claim 5
Dependent Claim
38 words
A circuit according to claim 3, having a normal operating state in which all the registers are in the first mode, and a test state in which each register is independently operable in the second or third mode.
Claim 6
Dependent Claim
29 words
A circuit according to claim 4 wherein, in the test state, each register is alternatively operable in a further mode in which it acts as a digital signature analyzer.
Claim 7
Dependent Claim
39 words
A circuit according to any one of claims 3, 4 or 5, having a further state in which all the registers (A-D) are connected together in series to form a serial shift path between a pair of external terminals.
Claim 8
Dependent Claim
62 words
A circuit according to any preceding claim, including an exclusive-OR network (15) connected to the outputs of selected stages of the register (10), and a multiplexer (14) for selecting either the output of the exclusive-OR network (15) or the output of the last stage (B7) of the register, for feeding back to the input of the first stage (BO) of the register.
Claim 9
Dependent Claim
19 words
A circuit according to claim 7 including an inverter circuit for selectively inverting the output of said multiplexer (14).
Claim 10
Independent Claim
51 words
A method of operating a circuit according to any preceding claim comprising the steps of loading into the register (10) a bit pattern consisting of a single bit of one binary value, the other bits all being of the other binary value, and then operating the register in the third mode.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.