EP0655788A1
Expired / Lapsed
EP
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A volatile memory cell
Assignee: STMicroelectronics SA
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Filing: 1993-11-29
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Granted: —
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Expires: 2013-11-29
Abstract
Abstract A semiconductor device (10) is described, incorporating electron traps E t at the interface (15) between a semiconductor substrate (13) and a gate dielectric layer (12) of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.
Inventors
- 👤 Alexander C/O Sgs-Thomson Microelec. Kalnitsky
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 06:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S438/00; Y10S438/91; Y10S438/953
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
54 words
A volatile memory cell characterized in that it comprises an insulated gate field effect transistor with charge traps (E t ) in its insulating layer (12), wherein said charge traps (E t ) have a peak density near or contiguous with the interface (15) between the semiconductor layer (13) and the insulating layer (12).
Claim 2
Dependent Claim
30 words
The volatile memory cell of claim 1, wherein the said charge traps (E t ) include a peak density of charge traps located within 1.0 nm of the interface (15).
Claim 3
Dependent Claim
30 words
The volatile memory cell of claim 1, wherein the said charge traps (E t ) include a peak density of charge traps located within 0.5-0.7 nm of the interface (15).
Claim 4
Dependent Claim
35 words
The volatile memory cell of claim 1, wherein the semiconductor layer (13) comprises P-type doped silicon and the insulating layer (12) comprises a layer of silicon dioxide containing implanted silicon ions forming said charge traps.
Claim 5
Dependent Claim
23 words
The volatile memory cell of claim 1 wherein the semiconductor layer (13) comprises Indium Phosphide and the insulating layer (15) comprises Silicon Nitride.
Claim 6
Dependent Claim
35 words
A volatile memory device comprising a plurality of memory cells (10) according to claim 1, arranged in rows and columns to allow addressing of individual cells by control circuitry connected to said volatile memory device.
Claim 7
Independent Claim
89 words
A method of manufacturing a volatile memory cell including the steps of: forming a layer of silicon dioxide (12) on a p-type monocrystalline silicon substrate (13); covering the silicon dioxide (12) layer with a layer of conductive material forming the gate electrode (18) of the volatile memory cell, characterized in that the method further comprises the step of implanting silicon ions into the silicon dioxide (12) layer so that said ions in the silicon dioxide layer will have a peak density near or contiguous with the silicon substrate .
Claim 8
Dependent Claim
18 words
The method of claim 7 characterized in that the implantation step is carried out before the covering step.
Claim 9
Dependent Claim
45 words
The method of claim 7 characterized in that said silicon dioxide dielectric layer has a thickness of between 22 and 32 nm, and that the implanting step is performed at an energy of 5 to 25keV, with an implant density of between 2x10¹⁴cm⁻² and 2x10¹⁶cm⁻².
References Cited (Backward Citations)
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