EP0621604A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for recovering floating-gate memory cells with low threshold voltage in flash-EEPROM memory devices
Assignee: STMicroelectronics SRL
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Filing: 1993-04-23
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Granted: —
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Expires: 2013-04-23
Abstract
Abstract A method for recovering flash-EEPROM memory cells (MC) with low threshold voltage is described. The method provide for the simultaneous application of a first voltage with a first prescribed value (V D ) and of a second voltage with a second prescribed value (V G ) to drain regions (D) of each of said memory cells (MC) and to gate regions (G) of the memory cell (MC) for a prescribed time interval suitable for submitting said memory cells (MC) to a prescribed threshold voltage shift. A reference ground voltage (GND) is concurrently applied to source regions (S) of said memory cells (MC).
Inventors
- 👤 Roberto Bez
- 👤 Lorenzo Fratin
- 👤 Alfonso Maurelli
- 👤 Daniele Cantarelli
- 👤 Paolo Ghezzi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 18:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A method for recovering floating-gate (FG) flash-EEPROM memory cells (MC) with low threshold voltage (V Ti1 , V Ti2 ), characterized in that a first voltage with a first prescribed value (V D ) and a second voltage with a second prescribed value (V G ) are simultaneously applied to drain regions (D) of the memory cell (MC) to be recovered and to gate regions (G) of the memory cell (MC) for a prescribed time interval suitable for submitting said memory cell (MC) to a prescribed threshold voltage shift, while a reference ground voltage (GND) is concurrently applied to source regions (S) of said memory cell (MC).
Claim 2
Dependent Claim
36 words
The method according to claim 1, characterized in that said method is performed on memory cells (MC) belonging to a memory array of a flash-EEPROM memory device which has been submitted to an electrical erasing procedure.
Claim 3
Dependent Claim
51 words
The method according to claim 2, characterized in that a preliminary step, performed after said electrical erasing procedure, is provided for detecting the existence of low threshold voltage memory cells (MC) and to consequently inhibit the application of said first voltage and second voltage if no such memory cell (MC) exists.
Claim 4
Dependent Claim
27 words
The method according to claim 2 or 3, characterized in that said first voltage and second voltage are alternatively applied to different sectors of said memory array.
Claim 5
Dependent Claim
28 words
The method according to claim 2 or 3, characterized in that said first voltage and second voltage are alternatively applied to different bit lines of said memory array.
Claim 6
Dependent Claim
30 words
The method according to claim 2 or 3, characterized in that said first voltage and second voltage are simultaneously applied to all the memory cells (MC) of said memory array.
Claim 7
Independent Claim
40 words
The method according to any of claims 1 to 6, characterized in that said first prescribed value (V D ) is chosen inside a first range of voltage values which are higher than said second prescribed value (V G ).
Claim 8
Independent Claim
40 words
The method according to any of claims 1 to 6, characterized in that said second prescribed value (V G ) is chosen inside a second range of voltage values which are lower than said first prescribed value (V D ).
References Cited (Backward Citations)
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