EP0520505A2
Expired / Lapsed
EP
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Nonvolatile semiconductor memory device and its operating method
Assignee: Toshiba Corp
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Filing: 1992-06-26
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Granted: —
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Expires: 2012-06-26
Abstract
Abstract In this invention, charges are extracted from the charge storage portion (111) by means of F-N tunnel current, and then avalanche hot carriers (-, +) are injected into the storage portion (111).
Inventors
- 👤 Kiyomi c/o Int.Prop.Div. K.K. Toshiba Naruke
- 👤 Tomoko c/o Int.Prop.Div. K.K. Toshiba Suzuki
- 👤 Seiji c/o Int.Prop.Div. K.K. Toshiba Yamada
- 👤 Etsushi c/o Int.Prop.Div. K.K. Toshiba Obi
- 👤 Masamitsu Int.Prop.Div. K.K. Toshiba Oshikiri
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:46
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; H; H10; H10B; H10B41/00; H10B41/30; G11C16/10; G11C16/14; G11C16/16; H10B41/10; H10B41/20; H10B41/40; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
211 words
A method of operating a nonvolatile semiconductor memory device including a semiconductor substrate (101) of a conductivity type having a source and drain regions (103, 105) of the opposite conductivity type for defining a channel region (107) therebetween, a gate insulator (109) provided on said channel region (107), electron-holding means (111) provided on said gate insulator (109), and a control gate (115) provided through an interlevel insulator (113) above said electron-holding means (111), said method characterized by comprising: discharging the electrons held in said electron-holding means (111) by applying a voltage between said control gate (115) and one of said source region (103), said drain region (105) and said substrate (101) so that one of said source (103), said drain region (105) and said substrate (101) region may be at a higher potential, and then applying a voltage between said source region (103) and said drain region (105) so that one of said drain region (105) and said source region (103) may be at a higher potential, while applying to said control gate (115) a voltage lower than a reading voltage, to generate avalanche hot carriers in the vicinity one of said drain region (105) and said drain region (103), and injecting these avalanche hot carriers into said electron-holding means (111).
Claim 2
Dependent Claim
46 words
The method according to claim 1, characterized in that said channel region (107), when said control gate (115) is applied with a voltage lower than the reading voltage, carries channel current smaller than that flowing when said control gate (115) is applied with the reading voltage.
Claim 3
Dependent Claim
35 words
The method according to claim 2, characterized in that said avalanche hot carriers are induced by the channel current flowing when said control gate (115) is applied with a voltage lower than the reading voltage.
Claim 4
Dependent Claim
136 words
The method according to claim 3, characterized in that said electron-holding means (111) is composed of a floating gate (111), and said gate insulator (109) is composed of an insulating film (109), and the electrons held in said electron-holding means (111) are discharged into one of said source region (103), said drain region (105) and said substrate (101) by applying a voltage between said control gate (115) and one of said source region (103), said drain region (105) and said substrate (101) so that one of said source region (103), said drain region (105) and said substrate (101) may be at a higher potential, to allow F-N tunnel current to flow through said insulating film (109) between said floating gate (111) and one of said source region (103), said drain region (105) and said substrate (101).
Claim 5
Dependent Claim
136 words
The method according to claim 4, characterized in that said avalanche carriers include avalanche hot electrons and avalanche hot holes, and said floating gate (111) has a balanced potential at which the amount of said avalanche hot electrons injected balances with the amount of said avalanche hot holes injected, and when the potential of said floating gate (111) after the discharge of said electrons into one of said source region (103), said drain region (105) and said substrate (101) is more positive than said balanced potential, said avalanche hot electrons are injected more into said floating gate (111) than said avalanche hot holes, whereas when the potential of said floating gate (111) is more negative than said balanced potential, said avalanche hot holes are injected more into said floating gate (111) than said avalanche hot electrons.
Claim 6
Dependent Claim
59 words
The method according to claim 5, characterized in that said electrons are discharged into one of said source region (103), said drain region (105) and said substrate (101) so that the potential of said floating gate (111) may be more positive than said balanced potential, to suppress the injection of said avalanche hot holes into said floating gate (111).
Claim 7
Dependent Claim
62 words
The method according to claim 6, characterized in that an impurity concentration of said channel region (107) is increased, thereby inhibiting a threshold voltage from decreasing due to the assistance of the potential of said floating gate (111) when the potential of said floating gate (111) is set at a positive value close to said balanced potential after said discharge of electrons.
Claim 8
Independent Claim
298 words
A method of erasing and programming the stored information in a nonvolatile semiconductor memory device, the device including a semiconductor substrate (101) of a conductivity type having a source and drain regions (103, 105) of the opposite conductivity type for defining a channel region (107) therebetween, a gate insulator (109) provided on said channel region (107), electron-holding means (111) provided on said gate insulator (109), and a control gate (115) provided through an interlevel insulator (113) above said electron-holding means (111), said method characterized by comprising the steps of: discharging the electrons held in said electron-holding means (111) by applying a voltage between said control gate (115) and one of said source region (103), said drain region (105) and said substrate (101) so that one of said source region (103), said drain region (105) and said substrate (101) may be at a higher potential, and then applying a voltage between said source region (103) and said drain region (105) so that one of said drain region (105) and said source region (103) may be at a higher potential, while applying to said control gate (115) a voltage lower than the reading voltage, to generate avalanche hot carriers in the vicinity one of said drain region (105) and said source region (103), and injecting these avalanche hot carriers into said electron-holding, means (111) to erase the stored information; and applying a voltage between said source region (103) and said drain region (105) so that one of said drain region (105) and source region (103) may be at a higher potential, while applying to said control gate (115) a voltage higher than a reading voltage, to accelerate channel electrons to generate channel hot electrons, and injecting these channel hot electrons into said electron-holding means (111) to program the stored information.
Claim 9
Dependent Claim
46 words
The method according to claim 8, characterized in that said channel region (107), when said control gate (115) is applied with a voltage lower than the reading voltage, carries channel current smaller than that flowing when said control gate (115) is applied with the reading voltage.
Claim 10
Dependent Claim
35 words
The method according to claim 9, characterized in that said avalanche hot carriers are induced by the channel current flowing when said control gate (115) is applied with a voltage lower than the reading voltage.
Claim 11
Dependent Claim
136 words
The method according to claim 10, characterized in that said electron-holding means (111) is composed of a floating gate (111), and said gate insulator (109) is composed of an insulating film (109), and the electrons held in said electron-holding means (111) are discharged into one of said source region (103), said drain region (105) and said substrate (101) by applying a voltage between said control gate (115) and one of said source region (103), said drain region (105) and said substrate (101) so that one of said source region (103), said drain region (105) and said substrate (101) may be at a higher potential to allow F-N tunnel current to flow through said insulating film (109) between said floating gate (111) and one of said source region (103), said drain region (105) and said substrate (101).
Claim 12
Dependent Claim
137 words
The method according to claim 11, characterized in that said avalanche hot carriers include avalanche hot electrons and avalanche hot holes, and said floating gate (111) has a balanced potential at which the amount of said avalanche hot electrons injected balances with the amount of said avalanche hot holes injected, and when the potential of said floating gate (111) after the discharge of said electrons into one of said source region (103), said drain region (105) and said substrate (101) is more positive than said balanced potential, said avalanche hot electrons are injected more into said floating gate (111) than said avalanche hot holes, whereas when the potential of said floating gate (111) is more negative than said balanced potential, said avalanche hot holes are injected more into said floating gate (111) than said avalanche hot electrons.
Claim 13
Dependent Claim
58 words
The method according to claim 12, characterized in that said electrons are discharged into one of said source region (103), said drain region (105) and said substrate so that the potential of said floating gate (111) may be more positive than said balanced potential, to suppress the injection of said avalanche hot holes into said floating gate (111).
Claim 14
Dependent Claim
62 words
The method according to claim 13, characterized in that an impurity concentration of said channel region (107) is increased, thereby inhibiting a threshold voltage from decreasing due to the assistance of the potential of said floating gate (111) when the potential of said floating gate (111) is set at a positive value close to said balanced potential after said discharge of electrons.
Claim 15
Independent Claim
310 words
A method of erasing and programming the stored information in a nonvolatile semiconductor memory device, the device including a semiconductor substrate (101) of a conductivity type having a source and drain regions (103, 105) of the opposite conductivity type for defining a channel region (107) therebetween, a gate insulator (109) provided on said channel region (107), electron-holding means (111) provided on said gate insulator (109), and a control gate (115) provided through an interlevel insulator (113) above said electron-holding means (111), said method characterized by comprising the steps of: applying a voltage between said source region and said drain region so that one of said drain region (105) and source region (103) may be at a higher potential, while applying to said control gate (115) a voltage lower than a reading voltage, to generate avalanche hot carriers in the vicinity one of said drain region (105) and said source region, and injecting these avalanche hot carriers into said electron-holding means (111), and then applying a voltage between said control gate (115) and one of said source region (103), said drain region (105) and said substrate (101) so that one of said source region (103), said drain region (105) and said substrate (101) may be at a higher potential, to discharge the electrons held in said electron-holding means (111) into one of said source region (103), said drain region (105) and said substrate (101) to erase the stored information; and applying a voltage between said source region (103) and said drain region (105) so that one of said drain region (105) and said source region (103) may be at a higher potential, while applying to said control gate (115) a voltage higher than the reading voltage, to accelerate channel electrons to generate channel hot electrons, and injecting these channel hot electrons into said electron-holding means (111) to program the stored information.
Claim 16
Dependent Claim
224 words
A nonvolatile semiconductor memory device characterized by comprising: a memory cell including a semiconductor substrate (101) of a conductivity type having a source and drain regions (103, 105) of the opposite conductivity type for defining a channel region (107) therebetween, a gate insulator (109) provided on said channel region (107), electron-holding means (111) provided on said gate insulator (109), and a control gate (115) provided through an interlevel insulator (113) above said electron-holding means (111); discharge means for applying a voltage between said control gate (115) and said source region (103), said drain region (105) and substrate (101) so that one of said source region (103), said drain region (105) and said substrate (101) may be at a higher potential, to discharge the electrons held in said electron-holding means (111) into one of said source region (103), said drain region (105) and said substrate (101); and injection means for applying a voltage between said source region (103) and said drain region (105) so that one of said drain region (105) and said source region (103) may be at a higher potential, while applying to said control gate (115) a voltage lower than a reading voltage, to generate avalanche hot carriers in the vicinity one of said drain region (105) and said source region (103), and injecting these avalanche hot carriers into said electron-holding means.
Claim 17
Dependent Claim
49 words
The nonvolatile semiconductor memory device according to claim 16, characterized in that said channel region (107), when said control gate (115) is applied with a voltage lower than the reading voltage, carries channel current smaller than that flowing when said control gate (115) is applied with the reading voltage.
Claim 18
Dependent Claim
38 words
The nonvolatile semiconductor memory device according to claim 17, characterized in that said avalanche hot carriers are induced by the channel current flowing when said control gate (115) is applied with a voltage lower than the reading voltage.
Claim 19
Dependent Claim
139 words
The nonvolatile semiconductor memory device according to claim 18, characterized in that said electron-holding means (111) is composed of a floating gate (111), and said gate insulator (109) is composed of an insulating film (109), and the electrons held in said electron-holding means (111) are discharged into one of said source region (103), said drain region (105) and said substrate (101) by applying a voltage between said control gate (115) and one of said source region (103), said drain region (105) and said substrate (101) so that one of said source region (103), said drain region (105) and said substrate (101) may be at a higher potential, to allow F-N tunnel current to flow through said insulating film (109) between said floating gate (111) and one of said source region (103), said drain region (105) and said substrate (101).
Claim 20
Dependent Claim
139 words
The nonvolatile semiconductor memory device according to claim 19, characterized in that said avalanche carriers include avalanche hot electrons and avalanche hot holes, and said floating gate (111) has a balanced potential at which the amount of said avalanche hot electrons injected balances with the amount of said avalanche hot holes injected, and when the potential of said floating gate (111) after the discharge of said electrons into one of said source region (103), said drain region (103) and said substrate (101) is more positive than said balanced potential, said avalanche hot electrons are injected more into said floating gate (111) than said avalanche hot holes, whereas when the potential of said floating gate (111) is more negative than said balanced potential, said avalanche hot holes are injected more into said floating gate (111) than said avalanche hot electrons.
Claim 21
Dependent Claim
24 words
The nonvolatile semiconductor memory device according to claim 20, characterized in that said injection means operates after said discharge means has completed its operation.
Claim 22
Dependent Claim
24 words
The nonvolatile semiconductor memory device according to claim 20, characterized in that said discharge means operates after said injection means has completed its operation.
Claim 23
Dependent Claim
52 words
The nonvolatile semiconductor memory device according to claim 21, characterized in that the potential of said floating gate (111) is set so as to be more positive than said balanced potential after said electrons have been discharged into one of said source region (103), said drain region (105) and said substrate (101).
Claim 24
Dependent Claim
82 words
The nonvolatile semiconductor memory device according to claim 23, characterized in that the impurity concentration in said channel region (107) is increased so as to raise the reading voltage dropped due to assist by the potential of said floating gate (111), when the potential of said floating gate (111) is set so as to be more positive than said balanced potential after said electrons have been discharged into one of said source region (103), said drain region (105) and said substrate (101).
Claim 25
Dependent Claim
52 words
The nonvolatile semiconductor memory device according to claim 22, characterized in that the potential of said floating gate (111) is set so as to be more positive than said balanced potential after said electrons have been discharged into one of said source region (103), said drain region (105) and said substrate (101).
Claim 26
Dependent Claim
82 words
The nonvolatile semiconductor memory device according to claim 25, characterized in that the impurity concentration in said channel region (107) is increased so as to raise the reading voltage dropped due to assist by the potential of said floating gate (111), when the potential of said floating gate (111) is set so as to be more positive than said balanced potential after said electrons have been discharged into one of said source region (103), said drain region (105) and said substrate (101).
References Cited (Backward Citations)
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