Circuit and method for conditioning erased eeproms prior to programming

Claim 3

The method of Claim 1 wherein said pulsed conditioning electric fields are directed away from said floating gates.

Claim 4

The method of Claim 1 wherein said pulsed conditioning electric fields are directed toward said floating gates.

Claim 5

The method of Claim 1 wherein said pulsed conditioning electric fields are alternately directed toward and away from said floating gates.

Claim 6

The method of Claim 1 wherein said pulsed conditioning electric fields are alternately directed away from and toward said floating gates.

Claim 7

The method of Claim 1 wherein all of said cells are programmed prior to erasing all of said cells.

Claim 8

The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is caused by a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array.

Claim 9

The method of Claim 1 wherein the field energy of each of said conditioning pulsed electric fields is caused by a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array and wherein the voltage of said pulsed voltage is less than 90% of the pulsed voltage used to program individual cells of said memory array.

Claim 10

The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is caused by a pulsed current applied between a wordline of said memory array and a bitline of said memory array.

Claim 11

The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is caused by a pulsed current applied between a wordline of said memory array and a bitline of said memory array and wherein the current of said pulsed current is less than 90% of the pulsed current used to program individual cells of said memory array.

Claim 12

The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is determined by the length of a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array.

Claim 13

The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is determined by the length of a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array and wherein the length of said pulsed voltage is less than 80% of the length of the pulsed voltage used to program individual cells of said memory array.

Claim 14

An electrically-erasable, electrically-programmable, read-only-memory array, comprising: rows and columns of memory cells, wherein all of the memory cells in a column are connected to bitlines and wherein all of the memory cells in a row are connected to a wordline, wherein each said memory cell has charge-storing means insulated from said wordline connected to said memory cell and insulated from each of said bitlines connected to said memory cell, wherein memory storage in said cell is determined by low and high voltage thresholds between bitlines connected to said cell, and wherein an initial low voltage threshold is set during manufacture of said cell; programming circuit means for providing programming voltages to said charge-storing means via said wordlines and bitlines; erasing circuit means for providing erasing voltages to said charge-storing means via said wordlines and bitlines; wherein said programming circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of a programming pulse for programming all of said memory cells.

Claim 15

An electrically-erasable, electrically-programmable, read-only-memory array, comprising: rows and columns of memory cells, wherein all of the memory cells in a column are connected to bitlines and wherein all of the memory cells in a row are connected to a wordline, wherein each said memory cell has charge-storing means insulated from said wordline connected to said memory cell and insulated from each of said bitlines connected to said memory cell, wherein memory storage in said cell is determined by low and high voltage thresholds between bitlines connected to said cell, and wherein an initial low voltage threshold is set during manufacture of said cell; programming circuit means for providing programming voltages to said charge-storing means via said wordlines and bitlines; erasing circuit means for providing erasing voltages to said charge-storing means via said wordlines and bitlines; wherein said programming circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of a programming pulse for programming all of said memory cells.

Claim 16

The array of Claim 13 wherein said erasing circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of an erasing pulse for erasing all of said memory cells.

Claim 17

An electrically-erasable, electrically-programmable, read-only-memory array, comprising: rows and columns of memory cells, wherein all of the memory cells in a column are connected to bitlines and wherein all of the memory cells in a row are connected to a wordline, wherein each said memory cell has charge-storing means insulated from said wordline connected to said memory cell and insulated from each of said bitlines connected to said memory cell, wherein memory storage in said cell is determined by low and high voltage thresholds between bitlines connected to said cell, and wherein an initial low voltage threshold is set during manufacture of said cell; programming circuit means for providing programming voltages to said charge-storing means via said wordlines and bitlines; erasing circuit means for providing erasing voltages to said charge-storing means via said wordlines and bitlines; wherein said erasing circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of an erasing pulse for erasing all of said memory cells.

Claim 18

An electrically-erasable, electrically-programmable, read-only-memory array, comprising: rows and columns of memory cells, wherein all of the memory cells in a column are connected to bitlines and wherein all of the memory cells in a row are connected to a wordline, wherein each said memory cell has charge-storing means insulated from said wordline connected to said memory cell and insulated from each of said bitlines connected to said memory cell, wherein memory storage in said cell is determined by low and high voltage thresholds between bitlines connected to said cell, and wherein an initial low voltage threshold is set during manufacture of said cell; programming circuit means for providing programming voltages to said charge-storing means via said wordlines and bitlines; erasing circuit means for providing erasing voltages to said charge-storing means via said wordlines and bitlines; wherein said erasing circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of an erasing pulse for erasing all of said memory cells.

Claim 19

The array of Claim 15 wherein said programming circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of a programming pulse for programming all of said memory cells.