Patent EP0614218A1 successfully refreshed from Google Patents.
EP0614218A1
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EP
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Method for manufacturing capacitor and MIS transistor
Assignee: NEC Corp
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Filing: 1994-03-01
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Granted: —
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Expires: 2014-03-01
Abstract
Abstract In a method for manufacturing a capacitor (C) having a lower electrode (8), an upper electrode (11A, 12A) and a dielectric layer (91, 92, 93) therebetween and a MIS transistor (Q n , Q P ) on the same semiconductor substrate (1), impurity ions are introduced by ion implantation into the upper electrode as well as a gate electrode of the MIS transistor.
Inventors
- 👤 Megumi C/O Nec Corporation Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/813
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
133 words
A method for manufacturing a capacitor and a MIS transistor by using a semiconductor substrate (1) including a capacitor forming area (C) and a MIS transistor forming area (Q n , Q p ), comprising the steps of: forming a field insulating layer (7) on the capacitor forming area of said semiconductor substrate; forming a capacitor lower electrode (8) on said field insulating layer; forming a capacitor dielectric layer (91, 92, 93) on said capacitor lower electrode; forming a gate insulating layer (10) on the MIS forming area of said semiconductor substrate; forming a capacitor upper electrode (11A, 12A) on said capacitor dielectric layer and a gate electrode (11B, 12B, 11C, 12C) on said gate insulating layer; and introducing impurity ions into said capacitor upper electrode and said gate electrode by ion implantation.
Claim 2
Dependent Claim
57 words
A method as set forth in claim 1, wherein said upper electrode and gate electrode forming step comprises the steps of: forming a polycrstalline silicon layer (11); forming a tungsten silicide layer (12) on said polycrystalline silicon layer; patterning said tungsten silicide layer and said polycrystalline silicon layer, to form said upper electrode and said gate electrode.
Claim 3
Dependent Claim
73 words
A method as set forth in claim 1, wherein said capacitor dielectric layer forming step comprises the steps of: forming a first silicon oxide layer (91); forming a silicon nitride layer (92) on said first silicon oxide layer; forming a second silicon oxide layer (93) on said silicon nitride layer; and patterning said second silicon oxide layer, said silicon nitride layer and said first silicon oxide layer, to form said capacitor dielectric layer.
Claim 4
Dependent Claim
35 words
A method as set forth in claim 3, wherein said capacitor lower electrode is made of polycrystalline silicon, said first silicon oxide layer forming step comprising a step of thermally growing said capacitor lower electrode.
Claim 5
Dependent Claim
26 words
A method as set forth in claim 3, wherein said second silicon oxide layer forming step comprises a step of thermally growing said silicon nitride layer.
Claim 6
Independent Claim
244 words
A method for manufacturing a capacitor, an N-channel MIS transistor and a P-channel MIS transistor by using a semiconductor substrate (1) including a capacitor forming area (C), an N-channel MIS transistor forming area (Q n ) and a P-channel MIS transistor forming area (Q p ) comprising the steps of: forming a field insulating layer (7) on the capacitor forming area of said semiconductor substrate; forming a capacitor lower electrode (8) on said field insulating layer; forming a capacitor dielectric layer (91, 92, 93) on said capacitor lower electrode; forming a gate insulating layer (10) on the N-channel MIS transistor forming area and the P-channel MIS forming area of said semiconductor substrate; forming a capacitor upper electrode (11A, 12A) on said capacitor dielectric layer, a gate electrode (11B, 12B) on said gate insulating layer of the N-channel MIS transistor forming area and a gate electrode (11C, 12C) on said gate insulating layer of the P-channel MIS transistor forming area; covering the P-channel MIS transistor forming area with a first photoresist pattern (13); introducing N-type impurity ions into the capacitor forming area and the N-channel MIS transistor forming area with a mask of said first photoresist pattern by ion implantation; removing said first photoresist pattern; covering the capacitor forming area and the N-channel MIS transistor forming area with a second photoresist pattern (15); and introducing P-type impurity ions into the P-channel MIS forming area with a mask of said second photoresist pattern by ion implantation.
Claim 7
Dependent Claim
58 words
A method as set forth in claim 6, wherein said upper electrode and gate electrode forming step comprises the steps of: forming a polycrstalline silicon layer (11); forming a tungsten silicide layer (12) on said polycrystalline silicon layer; and patterning said tungsten silicide layer and said polycrystalline silicon layer, to form said upper electrode and said gate electrode.
Claim 8
Dependent Claim
73 words
A method as set forth in claim 6, wherein said capacitor dielectric layer forming step comprises the steps of: forming a first silicon oxide layer (91); forming a silicon nitride layer (92) on said first silicon oxide layer; forming a second silicon oxide layer (93) on said silicon nitride layer; and patterning said second silicon oxide layer, said silicon nitride layer and said first silicon oxide layer, to form said capacitor dielectric layer.
Claim 9
Dependent Claim
35 words
A method as set forth in claim 8, wherein said capacitor lower electrode is made of polycrystalline silicon, said first silicon oxide layer forming step comprising a step of thermally growing said capacitor lower electrode.
Claim 10
Dependent Claim
26 words
A method as set forth in claim 8, wherein said second silicon oxide layer forming step comprises a step of thermally growing said silicon nitride layer.
Claim 11
Independent Claim
244 words
A method for manufacturing a capacitor, an N-channel MIS transistor and a P-channel MIS transistor by using a semiconductor substrate (1) including a capacitor forming area (C), an N-channel MIS transistor forming area (Q n ) and a P-channel MIS transistor forming area (Q p ), comprising the steps of: forming a field insulating layer (7) on the capacitor forming area of said semiconductor substrate; forming a capacitor lower electrode (8) on said field insulating layer; forming a capacitor dielectric layer (91, 92, 93) on said capacitor lower electrode; forming a gate insulating layer (10) on the N-channel MIS transistor forming area and the P-channel MIS forming area of said semiconductor substrate; forming a capacitor upper electrode (11A, 12A) on said capacitor dielectric layer, a gate electrode (11B, 12B) on said gate insulating layer of the N-channel MIS transistor forming area and a gate electrode (11C, 12C) on said gate insulating layer of the P-channel MIS transistor forming area; covering the capacitor forming area and the P-channel MIS transistor forming area with a first photoresist pattern (13'); introducing N-type impurity ions into the N-channel MIS transistor forming area with a mask of said first photoresist pattern by ion implantation; removing said first photoresist pattern; covering the N-channel MIS transistor forming area with a second photoresist pattern (15); and introducing P-type impurity ions into the capacitor forming area and the P-channel MIS forming area with a mask of said second photoresist pattern by ion implantation.
Claim 12
Dependent Claim
58 words
A method as set forth in claim 6, wherein said upper electrode and gate electrode forming step comprises the steps of: forming a polycrstalline silicon layer (11); forming a tungsten silicide layer (12) on said polycrystalline silicon layer; and patterning said tungsten silicide layer and said polycrystalline silicon layer, to form said upper electrode and said gate electrode.
Claim 13
Dependent Claim
73 words
A method as set forth in claim 11, wherein said capacitor dielectric layer forming step comprises the steps of: forming a first silicon oxide layer (91); forming a silicon nitride layer (92) on said first silicon oxide layer; forming a second silicon oxide layer (93) on said silicon nitride layer; and patterning said second silicon oxide layer, said silicon nitride layer and said first silicon oxide layer, to form said capacitor dielectric layer.
Claim 14
Dependent Claim
35 words
A method as set forth in claim 13, wherein said capacitor lower electrode is made of polycrystalline silicon, said first silicon oxide layer forming step comprising a step of thermally growing said capacitor lower electrode.
Claim 15
Dependent Claim
26 words
A method as set forth in claim 13, wherein said second silicon oxide layer forming step comprises a step of thermally growing said silicon nitride layer.
References Cited (Backward Citations)
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