Patent EP0559366A1 successfully refreshed from Google Patents.
EP0559366A1
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EP
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Stackable three-dimensional multiple chip semiconductor device and method for making the same
Assignee: Motorola Solutions Inc
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Filing: 1993-02-23
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Granted: —
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Expires: 2013-02-23
Abstract
Abstract A stackable three-dimensional multi-chip module (MCM) (59) can be manufactured where one chip carrier (42) is interconnected to another chip carrier (48) by solder joints (29). The top chip carrier (42) has solder balls (23) on a lower surface of the substrate (46). The lower chip carrier (48) has solder balls (16) on a top surface of the substrate (52) and solder balls (15) on a lower surface. A lid (60) can be used to seal a device (50), and the lid height would serve as a natural positive stand-off between the level of carriers, giving rise to hour glass shaped solder joints (29) which maximizes the fatigue life of the joints. Heat sinks to further enhance heat dissipation of the MCM can be easily accommodated in this stacking approach. Furthermore, each substrate is capable of carrying multiple chips, so the module incorporates planar chip density growth concurrently with the three-dimensional growth.
Inventors
- 👤 Paul T. Lin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 17:36
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/144; H10; H10W; H10W72/00; H10W72/071; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W90/00; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/877; H10W72/884; H10W90/20; H10W90/22; H10W90/288; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/53; Y10T29/5313; Y10T29/53174
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
131 words
A stackable semiconductor multiple chip module (8) comprising: a lower chip carrier substrate (12) of thermally conductive material having a plurality of solder bumps and pads (15 & 16) on both top and bottom surfaces of the carrier; a first semiconductor die (10) electrically and physically attached to the lower chip carrier substrate (12); an upper chip carrier substrate (20) of thermally conductive material having a top and a bottom surface; a plurality of solder bumps (23) on the bottom surface of the upper chip carrier substrate (20); and a second semiconductor die (18) mounted and electrically coupled to the upper chip carrier substrate (20), wherein the lower carrier (12) and the upper substrate (20) are electrically connected to each other by a joining of the solder bumps (23 & 16).
Claim 2
Dependent Claim
166 words
A stackable semiconductor multiple chip module (59) comprising: a lower chip carrier substrate (52) of thermally conductive material having a plurality of solder bumps and pads (15 & 16) on both top and bottom surfaces of the carrier substrate (52); a first semiconductor die (50) electrically and physically attached to the lower chip carrier substrate (52); an upper chip carrier substrate (46) of thermally conductive material having a top and a bottom surface; a plurality of solder bumps (23) on the bottom surface of the upper chip carrier substrate (46); a second semiconductor die (10) mounted and electrically coupled to the upper chip carrier substrate (46), wherein the lower chip carrier substrate (52) and the upper chip carrier substrate (46) are electrically connected to each other by solder joints (29); and a lid (60) capping the first semiconductor die (50) and serving as a positive stand-off to create hour-glass solder joints (29) between the upper chip carrier substrate (46) and the lower chip carrier substrate (52).
Claim 3
Dependent Claim
54 words
The semiconductor multiple chip module (8 or 59) according to claim 1 or 2 wherein the lower chip carrier substrate (12 or 52) and upper chip carrier substrate (20 or 46) are comprised of a material selected from the group consisting of: aluminum nitride, cofired ceramic, silicon wafer material, and printed circuit board material.
Claim 4
Dependent Claim
31 words
The semiconductor multiple chip module (8 or 59) according to claim 1 or 2 wherein the lower chip carrier substrate (12 or 52) further comprises dummy solder bumps for mechanical support.
Claim 5
Dependent Claim
59 words
The semiconductor multiple chip module (8 or 59) according to claim 1 or 2 wherein the solder bumps and pads (15 & 16) on the top and bottom surfaces of the lower chip carrier substrate (12 or 52) and the solder bumps (23) on the bottom of the upper chip carrier substrate (20 or 46) comprise different solder compositions.
Claim 6
Dependent Claim
35 words
The semiconductor multiple chip module (8 or 59) according to claim 1 or 2 wherein the lower chip carrier substrate (12 or 52) and upper chip carrier substrate (20 or 46) have through-hole vias (24).
Claim 7
Dependent Claim
29 words
The semiconductor multiple chip module (49 or 59) according to claim 1 or 2 wherein the lower chip carrier substrate (52) and upper chip carrier substrate (46) are multi-layered.
Claim 8
Independent Claim
201 words
A method for making a stackable semiconductor multiple chip module (25) comprising the steps of: providing a lower chip carrier substrate (26) of thermally conductive material; depositing a plurality of solder bumps and pads (15 & 16) on both top and bottom surfaces of the lower chip carrier substrate (26); mounting a first semiconductor die (10) onto the lower chip carrier substrate (26); electrically coupling the first semiconductor die (10) to the lower chip carrier substrate (26); placing a lid (28) over the first semiconductor die (10) to serve as a positive stand-off; providing an upper chip carrier substrate (30) of thermally conductive material, the upper chip carrier substrate having a top and a bottom surface; depositing a plurality of solder bumps (23) on the bottom surface of the upper chip carrier substrate (30); mounting a second semiconductor die (18) to the upper chip carrier substrate (30); electrically coupling the semiconductor die (18) to the upper chip carrier substrate (30); aligning the upper chip carrier substrate (30) to the lower chip carrier substrate (26) by position of the solder bumps and pads (15, 16, & 23); and reflowing the solder bumps and pads together to achieve physical and electrical connections (29).
Claim 9
Dependent Claim
52 words
The method of claim 8 wherein the steps of depositing solder bumps and pads (15 & 16) on the top and bottom surfaces of the lower chip carrier substrate (26) and solder bumps (23) on the bottom surface of the upper chip carrier substrate (30) further comprises depositing solder of different compositions.
Claim 10
Dependent Claim
18 words
The method of claim 8 further comprising the step of: attaching a heat sink (40) to a surface.
References Cited (Backward Citations)
JPS60194548A
Cited
EP0377932A2
Cited
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