Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
134 words
A controller for a First in First out memory (100), the controller comprising: detector logic (200) for detecting any difference between the number of addresses in the memory (100) into which data is written and the number of addresses in the memory from which data is read; and comparator logic (220) for generating a request data transfer signal in response to said difference becoming greater than or equal to a threshold; characterised in that the controller further comprises: threshold select logic (310,320) responsive to data having first and second portions being written to the memory (100), the threshold select logic setting the threshold to a first value when the first portion is being written and setting the threshold to a second value, greater than the first value, when the second portion is being written.
Claim 2
Dependent Claim
131 words
A controller as claimed in claim 1, wherein the threshold select logic (310,320) comprises: a control signal generator (Figure 7) for generating a binary control signal (320) in response to the data being written to the memory (100), the control signal generator (Figure 7) setting the control signal to a first level when the first portion is being written and setting the control signal to a second level when the second portion is being written; and a demultiplexor (310) for connecting a first register (210) storing the first value to the comparator logic (220) when the control signal (320) is set to the first level and connecting a second register (300) storing the second value to the comparator logic (220) when the control signal (320) is set to the second level.
Claim 3
Dependent Claim
129 words
A controller as claimed in claim 2, wherein the control signal generator (Figure 7) comprises: a counter (550) having a parallel output for counting addresses in the memory into which data is being written; a first decoder (560) connected to the parallel output for generating a first pulse in response to a first output count; a second decoder (560) connected to the parallel output for generating a second pulse in response to a second output count, the second output count being greater than the first; and a bistable latch (580) connected to the first and second decoders for setting the control signal (320) to the first level in repsonse to the first pulse and setting the control signal (320) to the second level in response to the second pulse.
Claim 4
Dependent Claim
67 words
A controller as claimed in any preceding claim wherein the detector logic comprises a up/down counter (200) having a parallel output, a count up clock input for incrementing the parallel output in response to data being written an address in the memory (100), and a count down clock input for decrementing the parallel output in response to data being read from an address in the memory (100).
Claim 5
Dependent Claim
51 words
A controller as claimed in any claim preceding claim 4 wherein the detector logic comprises subtractor logic (600) for subtracting a write address stored in a write address pointer (130) connected to the memory (100) from a read address stored in a read address pointer (140) connected to the memory (100).
Claim 6
Dependent Claim
16 words
A controller as claimed in any preceding claim wherein the first threshold is set to unity.
Claim 7
Dependent Claim
24 words
First in First Out memory apparatus comprising a First In First out memory (100) connected to a controller as claimed in any preceding claim.
Claim 8
Dependent Claim
33 words
A digital video capture system comprising: a video capture device (20), a display adaptor (30), and apparatus as claimed in claim 9 connected to the capture device (20) and the display adaptor (30).