Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
122 words
A data buffer for interfacing a digital input/output device to a data channel having a data transfer rate greater than said input/output device data transfer rate comprising: a data buffer (11,40) for simultaneously storing data from said input/output device (12) and reading said data to said data channel (14); and a buffer controller (24,19,49,48) for controlling load and unload operations of said data buffer, said buffer controller beginning an unload sequence to the higher speed data channel subsequent to a load sequence when a predetermined number of data bytes have been stored in said data buffer, said predetermined number being selected so that an entire data block is completely unloaded during the portion of said load sequence following said unload sequence beginning.
Claim 2
Dependent Claim
122 words
A data buffer for interfacing a digital input/output device to a data channel having a data transfer rate greater than said input/output device data transfer rate comprising: a data buffer (11,40) for simultaneously storing data from said input/output device (12) and reading said data to said data channel (14); and a buffer controller (24,19,49,48) for controlling load and unload operations of said data buffer, said buffer controller beginning an unload sequence to the higher speed data channel subsequent to a load sequence when a predetermined number of data bytes have been stored in said data buffer, said predetermined number being selected so that an entire data block is completely unloaded during the portion of said load sequence following said unload sequence beginning.
Claim 3
Dependent Claim
142 words
A data buffer of claim 1, comprising: means (18,25) for consecutively addressing each address of said buffer memory, and for storing each data byte received from said input/output device at each consecutive address during a load sequence; means (25,54) for unloading each data byte stored in said buffer memory during an unload sequence; a threshold register (22,66) for storing a threshold address of said buffer identifying a data byte which marks the start of an unload sequence for unloading said data buffer contents to said channel; and, a comparator (20,60) means connected to said data buffer and threshold register, said comparator enabling said means for unloading when a data buffer address equals said threshold register contents, whereby said means for unloading commences to unload said data buffer contents at a threshold selected to have said unloading sequence completed with said load sequence.
Claim 4
Dependent Claim
36 words
The data buffer of claim 2 further comprising means (50) connected to determine when said data buffer contents have been completely unloaded and subsequently reducing the rate at which data is unloaded from said data buffer.
Claim 5
Dependent Claim
28 words
The data buffer of claim 3 further comprising a register (55) for supplying the actual length of a data block transferred from said data buffer to said controller.
Claim 6
Dependent Claim
22 words
The data buffer of claim 4 further comprising means for updating said threshold based upon the actual length of said data block.
Claim 7
Dependent Claim
76 words
A data buffer of any of the claims 1 to 5, comprising: a microprocessor (29) connected to supply said threshold register with the identity of said data word which indicates the start of said transfer cycle, said microprocessor connected to receive a signal from said unload control for determining a new threshold identity for subsequent blocks of data based upon the length of a previous block of data transferred from said buffer memory to said channel.
Claim 8
Dependent Claim
66 words
The buffer interface of claim 6 wherein said microprocessor is programmed to calculate a threshold identity which will permit said buffer memory to be unloaded at a data rate corresponding to said channel rate while loading data at a rate determined by said peripheral device input/output data rate such that loading and unloading to and from said buffer memory are completed at substantially the same time.
Claim 9
Dependent Claim
31 words
The buffer interface of claim 7 wherein said microprocessor is programmed to release said channel until said data byte identified by said threshold register has been received by said buffer memory.
Claim 10
Dependent Claim
23 words
The buffer interface of claim 8 wherein said microprocessor is programmed to establish a new threshold identity based a previous data block length.
Claim 11
Independent Claim
159 words
A method for interfacing a data input/output device with a higher speed data channel comprising: storing in a buffer memory data from said data input/output device at a rate corresponding to the data rate of said data device; selecting a threshold identifying receipt of a particular data byte of a block of data to be stored, said threshold identifying the beginning of a data transfer cycle for unloading said data from said buffer memory to said channel, said threshold having a value which will permit said buffer memory contents to be completely transferred at the higher channel data rate to said channel during the remaining time additional data of said block of data is to be entered in said memory; and unloading said buffer memory at said higher channel data rate at a time said threshold is reached, whereby unloading of said buffer memory occurs during the remaining time said buffer memory is receiving data from said data device.
Claim 12
Independent Claim
159 words
A method for interfacing a data input/output device with a higher speed data channel comprising: storing in a buffer memory data from said data input/output device at a rate corresponding to the data rate of said data device; selecting a threshold identifying receipt of a particular data byte of a block of data to be stored, said threshold identifying the beginning of a data transfer cycle for unloading said data from said buffer memory to said channel, said threshold having a value which will permit said buffer memory contents to be completely transferred at the higher channel data rate to said channel during the remaining time additional data of said block of data is to be entered in said memory; and unloading said buffer memory at said higher channel data rate at a time said threshold is reached, whereby unloading of said buffer memory occurs during the remaining time said buffer memory is receiving data from said data device.
Claim 13
Dependent Claim
34 words
The method of claim 10 wherein said threshold is continually updated such that said buffer memory unloading time is substantially coincident with the remaining time said buffer memory receives data from said input/output device.
Claim 14
Dependent Claim
40 words
The method of claim 11 further comprising inhibiting unloading of said buffer memory contents at said channel rate when the number of data bytes unloaded from said buffer memory would exceed the number of data bytes loaded in said memory.
Claim 15
Dependent Claim
25 words
The method of claim 10 further comprising means for requesting connection to said channel when said buffer memory receives said byte identified by said threshold.