Multi-layer wiring structure in a semiconductor device and method of manufacturing the same

Claim 1

A multi-layer wiring structure in a semiconductor device, comprising a lower level wiring conductor of a desired pattern formed on a substrate, an interlayer insulating film formed on said substrate to completely cover said lower level wiring conductor, said interlayer insulating film having a thickness sufficiently larger than that of said lower level wiring conductor, said interlayer insulating fi'film having a through hole formed therethrough so as to reach an upper surface of said lower level wiring conductor, a first conducting film coated on a side wall surface of said through hole, an insulating film coated on said first conducting film, a second conducting film coated on said interlayer insulating film so as to surround said first conducting film, an electric conductor filled in said through hole in such a manner that one planar surface is constituted of an upper surface of said second conducting film, an upper end surface of said first conducting film, an upper end surface of said insulating film, and ah upper surface of said electric conductor filled in said through hole, and an upper level wiring conductor formed on said planar surface so that said upper level wiring conductor is electrically connected to said lower level wiring conductor through said electric conductor filled in said through hole.

Claim 4

A method for manufacturing a semiconductor device comprising: depositing an interlayer insulating film to completely cover a lower level wiring conductor of a desired pattern on a substrate, and planarizing the deposited interlayer insulating film; forming a first conducting film and a first insulating film on the planarized interlayer insulating film in the named order; forming a through hole by selectively removing said first insulating film, said first conducting film and said interlayer insulating film at a position where said lower level wiring conductor is to be connected to a possible upper level wiring conductor; forming a second conducting film and a second insulating film, in the named order, to cover said first insulating film and an inner surface of said through hole; etching back said second insulating film and said second conducting film so that said second insulating film and said second conducting film remain on only a side wall surface of said through hole; performing an electroplating process by supplying an electric current to said first conducting film, said second conducting film remaining on said side wall of said through hole and said lower level wiring conductor, so that an electrically conducting material is filled in the inside of said through hole to substantially the same height as a level of said first conducting film; etching back said first insulating film and a portion of said second conducting film and said second insulating film remaining on said side wall of said through hole until a surface of said first conducting film is exposed, so that a planarized surface is formed of said first conducting film, upper end portions of said second conducting film and said second insulating film remaining on said side wall of said through hole, and an upper surface of said electrically conducting material filled in said through hole; locating a photoresist on said planarized surface other than a place where a possible upper level wiring conductor is to be formed; performing an electroplating process by supplying an electric current to said first conducting film, said second conducting film remaining on said side wall of said through hole, said lower level wiring conductor and said electrically conducting material filled in said through hole, so that an upper level level wiring conductor is formed on at least said electrically conducting material filled in said through hole and a portion said first conducting film not covered by said photoresist; and removing said photoresist and said first conducting film other than a portion on which said upper level wiring conductor was formed.