Patent EP0515166A1 successfully refreshed from Google Patents.
EP0515166A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A data processor for performing simultaneous instruction retirement and backtracking
Assignee: Motorola Solutions Inc
•
Filing: 1992-05-20
•
Granted: —
•
Expires: 2012-05-20
Abstract
Abstract A data processing system (10) which has more general purpose physical registers than architectural (logical) registers. The system (10) uses a register inventory system (90) to monitor the allocation state changes of physical registers in a register file (37). As a sequencer (20) issues instructions, an indexed random access memory (RAM) (92) stores a copy of visible and allocation state bits for each of physical registers. When the sequencer (20) needs to perform a branch repair, the sequencer (20) must back up to the checkpoint where the branch instruction was issued. The visible and allocation bits for each physical register at this checkpoint are read out of the RAM (92). Using a predefined back-up deallocation relation, the register inventory system (90) determines which physical registers to deallocate and returns those physical registers to a free pool. The register inventory system (90) allows the sequencer (20) to simultaneously retire any instructions which were completed, and discard any instructions marked by the back-up process.
Inventors
- 👤 Michael C. Shebanow
- 👤 Mitchell Alsup
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3818; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
140 words
In a data processing system (10) having a predetermined number of execution units (25-30) for simultaneously executing a plurality of instructions issued by a sequencer (20), and a plurality of numbered physical registers in a register file (37) for selectively storing information resulting from execution by said execution units (25-30) of each of said predetermined number of instructions, means (90) for performing simultaneous instruction retirement and back tracking comprising: first means (94,96,97) for monitoring an allocation state change of each of said physical registers, in response to said sequencer (20) advancing from a first consistent checkpoint to a subsequent retirement checkpoint; and second means (76,100,101,108) for simultaneously monitoring said allocation state change of each of said physical registers, in response to said sequencer (20) discarding a stream of instructions issued between a first back-up checkpoint and a subsequent issue checkpoint.
Claim 2
Dependent Claim
169 words
In a data processing system (10) having a predetermined number of execution units (25-30) for simultaneously executing a plurality of instructions issued by a sequencer (20), and a plurality of numbered physical registers in a register file (37) for selectively storing a plurality of data values resulting from execution by said execution units (25-30) of each of said predetermined number of instructions, means for performing simultaneous instruction retirement and back tracking comprising: first means (94,96,97) for monitoring an allocation state change of each of said physical registers, in response to said sequencer (20) advancing from a first consistent checkpoint to a subsequent retirement checkpoint; second means (76,100,101,108) for monitoring said allocation state change of each of said physical registers, in response to said sequencer (20) discarding a stream of instructions issued between a backup checkpoint and a subsequent issue checkpoint; and wherein none of said plurality of data values are transferred between said numbered physical registers during monitoring performance of said first means (94,96,97) or said second means (76,100,101,108).
Claim 3
Dependent Claim
329 words
In a data processing system (10) having a predetermined number of execution units (25-30) for simultaneously executing a plurality of instructions issued by a sequencer (20), and a plurality of numbered physical registers in a register file (37) for selectively storing a plurality of data values resulting from execution by said execution units (25-30) of each of said predetermined number of instructions, means (90) for performing simultaneous instruction retirement and back tracking comprising: storage means (76,92,94,96,100) coupled to a unique physical register (48) for selectively retrieving and storing a first set of bits, in response to a first control signal from said sequencer (20), and for selectively retrieving and storing a second set of bits in response to a second control signal from said sequencer (20); retirement means (97) for coupled to said storage means (76, 92,94,96,100) for monitoring an allocation state change of each of said physical registers, in response to said sequencer (20) advancing from a first consistent checkpoint to a subsequent retirement checkpoint, said retirement means (97) retrieving said first set of bits and logically combining said first set of bits to determine whether to deallocate said unique physical register (48) at a retirement checkpoint, and providing a first output deallocation signal representative thereof; backtrack means (101,108) for simultaneously monitoring said allocation state change of each of said physical registers, in response to said sequencer (20) discarding a stream of instructions issued between a first checkpoint and a subsequent issue checkpoint, said backtrack means (101,108) retrieving said second set of bits and logically combining said second set of bits to determine whether to deallocate said unique physical register (48) at a back-up checkpoint, and providing a second output deallocation signal representative thereof; and; means (103) coupled to said retirement means (97) and said backtrack means (101,108) for logically combining said first output deallocation signal and said second output deallocation signal to define a set of physical registers which are available for reallocation by said sequencer (20).
References Cited (Backward Citations)
EP0301220A2
Cited
EP0463628A2
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.