EP0463628A2
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EP
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One cycle register mapping
Assignee: Compaq Computer Corp
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Filing: 1991-06-28
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Granted: —
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Expires: 2011-06-28
Abstract
Abstract A register map having a free list of available physcial locations in a register file, a log containing a sequential listing of logical registers changed during a predetermined number of cycles, a back-up map associating the logical registers with corresponding physical homes at a back-up point in a computer pipeline operation and a predicted map associating the logical registers with corresponding physcial homes at a current point in the computer pipeline operation. A set of valid bits is associated with the maps to indicate whether a particular logical register is to be taken from the back-up map or the predicted map indication of a corresponding physical home. The valid bits can be "flash cleared" in a single cycle to back-up the computer pipeline to the back-up point during a trap event.
Inventors
- 👤 Simon C. Steely Jr.
- 👤 David J. Sager
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 18:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
175 words
An arrangement for mapping m logical registers used in the execution of instructions processed through a computer pipeline, comprising: a register file having n locations for storing values, said locations being physical homes of the m logical registers, where m<n; and a register map coupled to the register file and receiving instructions as input and generating mapped instructions as output to the register file, the register map comprising: a free list that contains a number of locations p, each said free list location containing a register file location and which indicates which of said register file locations are free for use in a current cycle; a log that contains a sequential listing of which of the m logical registers was changed in each of the last t cycles; a backup map that contains a map associating m of the n physical homes to the m logical registers at a backup point; and a predicted map that contains a map associating m of the n physical homes to the m logical registers at a current point.
Claim 2
Dependent Claim
37 words
The arrangement of Claim 1, further comprising a set of valid bits that indicate whether the physical home associated with a logical register should be taken from the backup map or the predicted map when mapping registers.
Claim 3
Independent Claim
160 words
A method of maintaining a mapping of m logical registers to n physical homes contained in a register file for instructions processed in a computer pipeline, comprising: receiving an instruction to be mapped in a register map; maintaining a free list that indicates which of the physical homes in the register file are free for use in a current cycle; maintaining in a log a sequential listing of which of the m logical registers was changed in each of the last t cycles; maintaining in a backup map a map of the physical home of each of the m logical registers at a backup point; maintaining in a predicted map a map of the physical home of each of the m logical registers at a current point; maintaining a set of valid bits that indicate whether the physical home associated with a specific logical register is to be taken from the backup map or the predicted map when mapping registers.
Claim 4
Dependent Claim
42 words
The method of Claim 3, further comprising the step of flash-clearing the set of valid bits to thereby indicate that the correct physical home for a logical register is to be taken from the backup map when backing up the instruction stream.
Claim 5
Dependent Claim
50 words
The method of Claim 3, wherein the step of maintaining a freelist includes storing a present physical home for the logical register being changed in a first location in the freelist, and assigning a new physical home to the logical register being changed from a second location in the freelist.
Claim 6
Dependent Claim
49 words
The method of Claim 5, wherein the step of maintaining a freelist further includes aging a present physical home that is stored for a period of time equal to a backup time before assigning the aged physical home as a new physical home to the logical register being changed.
Claim 7
Dependent Claim
38 words
The method of Claim 6, wherein the step of maintaining in a predicted map includes storing the new physical home for the logical register being changed into the predicted map at a location indexed by the logical register.
Claim 8
Dependent Claim
30 words
The method of Claim 7, wherein the step of maintaining a set of valid bits includes setting a valid bit that corresponds to the logical register that is being changed.
Claim 9
Dependent Claim
68 words
The method of Claim 8, wherein the step of maintaining in a backup map includes addressing the log to identify the logical register that was changed a backup time ago, identifying from the freelist the physical home that was assigned to the logical register that was changed a backup time ago, and storing this physical home into the backup map at a location indexed by the logical register.
Claim 10
Independent Claim
167 words
A method of assigning physical homes to logical registers used in executing instructions processed through a computer pipeline, comprising: receiving in a register mapping station a new instruction to be executed during a current cycle; identifying the logical register that is being written to in the current cycle; identifying the logical registers that are being read in the current cycle; determining the state of valid bits associated with the logical registers that are being read in the current cycle; providing the physical home for each logical register that is being read in the current cycle from a backup map if the state of the valid bit for that logical register is not set, and from a predicted map if the state of the valid bit for that logical register is set; and assigning from a freelist a new physical home to the logical register that is being written to in the current cycle; wherein the number of physical homes is greater than the number of logical registers.
References Cited (Backward Citations)
No citation records indexed.
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