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EP0505073A1
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Video signal gradation corrector
Assignee: Panasonic Holdings Corp
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Filing: 1992-03-10
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Granted: —
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Expires: 2012-03-10
Abstract
Abstract In a video signal gradation corrector used in a television receiver, an output of a look-up table memory (11) is supplied to a constant-multiplication circuit (31), an output signal of the constant-multiplication circuit (31) and an output signal of a look-up table operating circuit (10) are added by an adder (32), and the result of addition is set into the look-up table memory (11). Further, a video scene change detecting circuit (33) is provided between an output terminal of the look-up table operating circuit (10) and a coefficient control terminal of the constant-multiplication circuit (31), and a coefficient of the constant-multiplication circuit (31) is changed in accordance with a change in video scene. Thereby, a correction is made which is not affected by noises, is stable and smooth, and follows the change in video scene.
Inventors
- 👤 Toshiaki Tsuji
- 👤 Atsuhisa Kageyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:28
CPC Classifications
G; G06; G06T; G06T5/00; G06T5/90; G06T5/92; H; H04; H04N; H04N5/00; H04N5/14; H04N5/147; G06T5/40; H04N19/00; H04N19/10; H04N19/134; H04N19/142; H04N19/169; H04N19/179; H04N19/85; H04N19/87; H04N5/20
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
249 words
A gradation corrector comprising a hystogram memory for storing a hystogram of a video luminance signal, a hystogram operating circuit for receiving an output signal of the hystogram memory to extract a feature of the hystogram from data stored in the hystogram memory, a limiter/adder circuit connected to an output terminal of the hystogram operating circuit for processing the data of the hystogram memory, an accumulation control register circuit and a normalization control register circuit each connected to an output terminal of the hystogram operating circuit, a hystogram accumulation circuit for receiving an output signal of the hystogram memory and an output signal of the accumulation control register circuit to make a cumulative addition for the processed data of the hystogram memory, a cumulative hystogram memory for storing the result of cumulative addition, a look-up table operating circuit for receiving an output signal of the cumulative hystogram memory and an output signal of the normalization control register circuit to normalize data of the cumulative hystogram memory, a look-up table memory for storing the result of normalization, a buffer connected to an output terminal of the hystogram memory for storing hystogram data obtained in a vertical scanning interval preceding by one interval, a constant-multiplication circuit connected to an output terminal of the buffer, an adder for adding output data of the hystogram memory and output data of the constant-multiplication circuit and outputting the result of addition to the hystogram memory, and a timing control circuit for controlling the above-mentioned circuits.
Claim 2
Dependent Claim
284 words
A gradation corrector comprising a hystogram memory for storing a hystogram of a video luminance signal, a hystogram operating circuit for receiving an output signal of the hystogram memory to extract a feature of the hystogram from data stored in the hystogram memory, a limiter/adder circuit connected to an output terminal of the hystogram operating circuit for processing the data of the hystogram memory, an accumulation control register circuit and a normalization control register circuit each connected to an output terminal of the hystogram operating circuit, a hystogram accumulation circuit for receiving an output signal of the hystogram memory and an output signal of the accumulation control register circuit to make a cumulative addition for the processed data of the hystogram memory, a cumulative hystogram memory for storing the result of cumulative addition, a look-up table operating circuit for receiving an output signal of the cumulative hystogram memory and an output signal of the normalization control register circuit to normalize data of the cumulative hystogram memory, a look-up table memory for storing the result of normalization, a buffer connected to an output terminal of the hystogram memory for storing hystogram data obtained in a vertical scanning interval preceding by one interval, a video scene change detecting circuit connected to the output terminal of the hystogram memory for detecting a change in video scene, a constant-multiplication circuit connected to an output terminal of the buffer and the coefficient of which is changed by an output signal of the video scene change detecting circuit, an adder for adding output data of the hystogram memory and output data of the constant-multiplication circuit and outputting the result of addition to the hystogram memory, and a timing control circuit.
Claim 3
Dependent Claim
224 words
A gradation corrector comprising a hystogram memory for storing a hystogram of a video luminance signal, a hystogram operating circuit for receiving an output signal of the hystogram memory to extract a feature of the hystogram from data stored in the hystogram memory, a limiter/adder circuit connected to an output terminal of the hystogram operating circuit for processing the data of the hystogram memory, an accumulation control register circuit and a normalization control register circuit each connected to an output terminal of the hystogram operating circuit, a hystogram accumulation circuit for receiving an output signal of the hystogram memory and an output signal of the accumulation control register circuit to make a cumulative addition for the processed data of the hystogram memory, a cumulative hystogram memory for storing the result of cumulative addition, a look-up table operating circuit for receiving an output signal of the cumulative hystogram memory and an output signal of the normalization control register circuit to normalize data of the cumulative hystogram memory, an adder for adding output data of the look-up table operating circuit and output data of a constant-multiplication circuit, a look-up table memory for storing output data of the adder, the constant-multiplication circuit for multiplying data of the look-up table memory by a constant and outputting the result of multiplication to the adder, and a timing control circuit.
Claim 4
Dependent Claim
266 words
A gradation corrector comprising a hystogram memory for storing a hystogram of a video luminance signal, a hystogram operating circuit for receiving an output signal of the hystogram memory to extract a feature of the hystogram from data stored in the hystogram memory, a limiter/adder circuit connected to an output terminal of the hystogram operating circuit for processing the data of the hystogram memory, an accumulation control register circuit and a normalization control register circuit each connected to an output terminal of the hystogram operating circuit, a hystogram accumulation circuit for receiving an output signal of the hystogram memory and an output signal of the accumulation control register circuit to make a cumulative addition for the processed data of the hystogram memory, a cumulative hystogram memory for storing the result of cumulative addition, a look-up table operating circuit for receiving an output signal of the cumulative hystogram memory and an output signal of the normalization control register circuit to normalize data of the cumulative hystogram memory, an adder for adding output data of the look-up table operating circuit and output data of a constant-multiplication circuit, a look-up table memory for storing output data of the adder, a video scene change detecting circuit connected to an output terminal of the look-up table operating circuit for detecting a change in video scene, the constant-multiplication circuit for multiplying data of the look-up table memory by a constant and the coefficient of which is changed by an output signal of the video scene change detecting circuit and outputting the result of multiplication to the adder, and a timing control circuit.
References Cited (Backward Citations)
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