Patent FR882743A successfully refreshed from Google Patents.
US3979555A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Histogram equalization system for display improvement
Assignee: Raytheon Co
•
Filing: 1975-05-27
•
Granted: 1976-09-07
•
Expires: 1995-05-27
Abstract
Abstract A histogram equalization system that adaptively redistributes the intensity coding of the video in order to provide an equal number of elements at all display intensity levels. The actual amplitude value of the input video as stored in an integrator, for example, is utilized to address a random access memory which originally is loaded with all zeros. The memory is organized such that there are as many addressable words as there are possible video intensity values carried in the integrator thereby building up a histogram within the memory. Upon completion of the histogram, a constant equal to the number of picture elements corresponding to the data used to form the histogram divided by the number of values to which it is desired to truncate, is utilized in a comparator as the histogram memory is sequentially read out and accumulated to determine the truncation points. A latching circuit is filled with the truncation point values and these points are used in a truncation logic circuit responding to the input video signal to reduce the number of video bits. The truncated signal increases the sensitivity to localized signal variations of a scene so as to increase the detail of the gray scale region requiring additional intensity codes.
Inventors
- 👤 Eugene W. Opittek
- 👤 David J. Ketcham
- 👤 Edward J. Dragavon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:36
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20; G; G01; G01S; G01S7/00; G01S7/02; G01S7/04; G01S7/06
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
171 words
A system responsive to a signal source of amplitude data of a first number of bits to develop a truncated signal having a second and lesser number of bits comprising: a histogram memory addressable with the value of said amplitude data for storing at each address the number of address occurrences during a first period, read address generator means coupled to said histogram memory for applying sequential addresses thereto during a second period, accumulating means coupled to said histogram memory for accumulating the number of occurrences read from said memory, during said second period, comparator means coupled to said accumulator means for responding when the accumulated occurrences equals a predetermined value equal to a selected fraction of the signals addressing said memory during said first period, truncation point latch means coupled to said comparator and to said read address generator for storing the truncation points; and truncation logic means coupled to said signal source and to said truncation point latch means for developing truncated signals of said second number of bits.
Claim 2
Independent Claim
171 words
A system responsive to a signal source of amplitude data of a first number of bits to develop a truncated signal having a second and lesser number of bits comprising: a histogram memory addressable with the value of said amplitude data for storing at each address the number of address occurrences during a first period, read address generator means coupled to said histogram memory for applying sequential addresses thereto during a second period, accumulating means coupled to said histogram memory for accumulating the number of occurrences read from said memory, during said second period, comparator means coupled to said accumulator means for responding when the accumulated occurrences equals a predetermined value equal to a selected fraction of the signals addressing said memory during said first period, truncation point latch means coupled to said comparator and to said read address generator for storing the truncation points; and truncation logic means coupled to said signal source and to said truncation point latch means for developing truncated signals of said second number of bits.
Claim 3
Dependent Claim
55 words
The combination of claim 1 in which said comparator means includes storage means to provide said predetermined value equal to the number of picture elements in a selected portion of an image, with said selected portion represented by the plurality of data signals utilized in the histogram memory for the formation of an image histogram.
Claim 4
Dependent Claim
28 words
The combination of claim 2 in which said truncation point latch means includes a plurality of registers equal to the number of intensity levels of said truncated signal.
Claim 5
Dependent Claim
84 words
The combination of claim 3 in which said truncation point latch means includes gating means coupled to the output of each register, and sequencing means coupled to said registers for sequentially gating the stored truncation points therefrom, and in which said truncation logic means includes a comparator coupled to said signal source and to the gating means at the output of each register and includes a counter coupled to said comparator and counting in sequence with said sequencing means for providing said truncated signals.
Claim 6
Dependent Claim
59 words
The combination of claim 4 in which each of said registers includes an input gate and said read address generator means is coupled to the input gates of said registers and further including an address counter coupled to the input gates of said registers for sequentially addressing a different register for each truncation point defined by said comparator means.
Claim 7
Dependent Claim
127 words
A histogram equalization system responsive to a source of video amplitude signals received during a range period to form truncated video signals comprising: integrator means for sequentially storing the video signals received during a plurality of range periods, a histogram memory coupled to said integrator means for forming a histogram, accumulator means coupled to said histogram memory for accumulating the contents of said histogram memory for defining truncation intensity levels, storage means coupled to said accumulator means for storing said truncation intensity levels; and truncation logic means coupled to said integrator means and to said storage means for comparing the video amplitude of each signal with the truncation intensity levels to form truncated video signals representative of the video signals received during said plurality of range periods.
Claim 8
Dependent Claim
127 words
A histogram equalization system responsive to a source of video amplitude signals received during a range period to form truncated video signals comprising: integrator means for sequentially storing the video signals received during a plurality of range periods, a histogram memory coupled to said integrator means for forming a histogram, accumulator means coupled to said histogram memory for accumulating the contents of said histogram memory for defining truncation intensity levels, storage means coupled to said accumulator means for storing said truncation intensity levels; and truncation logic means coupled to said integrator means and to said storage means for comparing the video amplitude of each signal with the truncation intensity levels to form truncated video signals representative of the video signals received during said plurality of range periods.
Claim 9
Dependent Claim
37 words
The combination of claim 6 in which said accumulator means includes read addressing means coupled to said histogram memory for sequentially reading out the contents thereof so as to accumulate the frequency of occurrences of said histogram.
Claim 10
Dependent Claim
82 words
The combination of claim 7 in which the video amplitude signals received from said integrator each have a first number of bits and the truncated video signals each have a second and lesser number of bits, and the video amplitude signals each represent a picture element, for display, said accumulator means further including comparator means coupled to said storage means, and a source of a signals representative of the number of picture elements at each truncation point coupled to said comparator means.
Claim 11
Dependent Claim
41 words
The combination of claim 8 in which said truncation logic means includes a comparator coupled to said integrator and to said storage means, and counter means coupled to said comparator and to said storage means to form said truncated video signals.
Claim 12
Dependent Claim
107 words
A histogram equalization system comprising: a source of digital signals representing amplitude, memory means coupled to said source for being addressed by the amplitude value of said digital signals, means to add a one to the contents of each addressed cell of said memory means, accumulator means coupled to said memory for storing the contents of said cell when read therefrom, comparator means coupled to said accumulator means for developing truncation point signals, truncation point storage means coupled to said accumulator means for storing said truncation point signals, and logic means coupled to said truncation point storage means and to said source for developing truncated digital signals.
Claim 13
Dependent Claim
107 words
A histogram equalization system comprising: a source of digital signals representing amplitude, memory means coupled to said source for being addressed by the amplitude value of said digital signals, means to add a one to the contents of each addressed cell of said memory means, accumulator means coupled to said memory for storing the contents of said cell when read therefrom, comparator means coupled to said accumulator means for developing truncation point signals, truncation point storage means coupled to said accumulator means for storing said truncation point signals, and logic means coupled to said truncation point storage means and to said source for developing truncated digital signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-07 | 1980-03-08 | 1980-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-07 | 1984-03-08 | 1984-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-07 | 1988-03-08 | 1988-09-07 | $7700.00 | Window Closed / Lapsed |