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EP0490243A1
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BICMOS tri-state output buffer
Assignee: HP Inc
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Filing: 1991-12-03
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Granted: —
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Expires: 2011-12-03
Abstract
Abstract A BiCMOS tri-state output buffer including logic for preventing reverse biasing of the output transistors. A pair of bipolar transistors (12, 14) are configured as a totem-pole output circuit. A transmission gate (38) provides a controllable-resistance current path between the base and emitter of the emitter-follower transistor (12). Logic circuitry (26, 54, 44, 46) causes the resistance of the path to go low when the circuit is in its disabled or high-impedance "off" state and when the output undergoes a high-to-low transition when the circuit is not disabled, thereby preventing reverse bias of the emitter-follower output transistor.
Inventors
- 👤 Robert Joly
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826; H03K17/00; H03K17/08; H03K17/081; H03K17/08112; H03K19/003; H03K19/00307; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
182 words
A tri-state output buffer comprising: a first bipolar output transistor (12) having a collector electrically coupled to a first power terminal (25), an emitter electrically coupled to an output node (10), and a base; a second bipolar output transistor (14) having a collector electrically coupled to the output node (10), an emitter electrically coupled to a second power terminal (25'), and a base; signal means (48, 50), electrically coupled to the bases of the output transistors, responsive to an input signal (V IN ) to cause the output transistors (12, 14) to provide at the output node (10) an output signal corresponding with the input signal; enable means (26, 36), electrically coupled to the bases of the output transistors, responsive to an enable signal (E, E ¯ ) to override the signal means and cause the output node (10) to assume a high impedance state when the enable signal assumes a "disable" value; and circuit means operative to prevent reverse bias between the base and the emitter of the first transistor (12) whenever the output node is in the high impedance state.
Claim 2
Dependent Claim
52 words
A tri-state output buffer as in claim 1 wherein the circuit means comprises a variable-resistance current path (38) between the base and the emitter, and means (26, 44, 46) for causing the path (38) to assume a low resistance and thereby prevent reverse bias when the enable signal assumes the "disable" value.
Claim 3
Dependent Claim
55 words
A tri-state output buffer as in claim 2 wherein the circuit means further comprises means (54, 44, 46) for causing the path (38) to assume a low resistance and thereby prevent reverse bias during a high-to-low transition in the value of the output signal when the output node (10) is not in a high-impedance state.
Claim 4
Dependent Claim
18 words
A tri-state output buffer as in claim 2 or 3 wherein the current path comprises a transmission gate.
Claim 5
Dependent Claim
122 words
A tri-state output buffer as in claim 4 wherein the circuit means comprises an inverter stage (44, 46) and first (54) and second (26) transistors in parallel connection between the first power terminal (25) and a first control node (60), the first transistor (54) having a gate connected to receive the input signal (V IN ) and the second transistor (26) having a gate connected to receive the enable signal, the control node (60) being connected to one gate of the transmission gate (38) and to an input of the inverter stage (44, 46), the output of the inverter stage being connected to another gate of the transmission gate (38) whereby the first and second transistors (54, 26) control the transmission gate.
Claim 6
Dependent Claim
82 words
A tri-state output buffer as in claim 5 wherein the circuit means comprises third (56) and fourth (34) transistors in parallel connection between the second power terminal (25') and a second control node (58) and a second transmission gate (32) having inputs that receive the enable/disable signal (E, E ¯ ), the second transmission gate (32) operative to electrically couple the first (60) and second (58) nodes when the buffer is enabled and to decouple the nodes when the buffer is disabled.
Claim 7
Independent Claim
135 words
A method for operating a tri-state output buffer of the type that includes an input port for receiving an input signal and an enable port for receiving an enable/disable signal and first and second bipolar transistors in series between first and second power terminals, the first transistor having a collector electrically coupled to the first power terminal, an emitter electrically coupled to an output node, and a base, the second transistor having a collector electrically coupled to the output node and an emitter electrically coupled to the second power terminal, the method comprising: electrically coupling the base and emitter of the first transistor to prevent any reverse bias if the enable/disable signal assumes a "disable" value; and electrically decoupling the base and emitter of the first transistor if the enable/disable signal assumes an "enable" value.
Claim 8
Dependent Claim
44 words
A method as in claim 7 and further comprising electrically coupling the base and emitter of the first transistor to prevent any reverse bias during a high-to-low transition of the output signal if during said transition the enable/disable signal is at the "enable" value.
References Cited (Backward Citations)
EP0316793A2
Cited
EP0383554A2
Cited
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