Interconnect and method of manufacture for semiconductor devices

Claim 2

The contact structure as recited in claim 1 further comprising a second polysilicon region disposed on said substrate at a location displaced from said first polysilicon contact region, said second polysilicon region comprising at least one sidewall having oxide thereon, said metallic region extending along and in contact with said substrate from said oxide on said at least one sidewall to said first contact sidewall.

Claim 3

The contact structure as recited in claim 1 wherein said metallic region is a metal silicide region.

Claim 4

A contact structure as recited in claim 2 wherein said second polysilicon region comprises: a) oxide on a second sidewall thereof; and b) silicide on an upper surface of said second polysilicon region between said oxide sidewalls.

Claim 5

The contact structure as recited in claim 1 wherein said metallic region further covers and is in contact with a second sidewall.

Claim 6

The contact structure as recited in claim 1 wherein said first sidewall extends down to a field oxide region in said substrate, said metallic region terminating on said field oxide region.

Claim 7

The contact structure as recited in claim 1 wherein said first polysilicon contact is selected from the group base contacts of bipolar transistors, collector contacts of bipolar transistors, source contacts of field effect transistors, and drain contacts of field effect transistors.

Claim 8

The contact structure as recited in claim 2 wherein said second polysilicon region is selected from the group emitters of bipolar transistors, and gates of field effect transistors.

Claim 9

The contact structure as recited in claim 3 wherein said second polysilicon region is an emitter of a bipolar transistor, said first polysilicon contact region is a base contact of a bipolar transistor, and said base is contacted by said silicide from said first vertical sidewall to said oxide on said second polysilicon region.

Claim 10

The contact structure as recited in claim 2 wherein said first polysilicon region is a source or drain of a field effect transistor, said second polysilicon region is a gate of said field effect transistor, and said silicide contacts said source or said drain from said first polysilicon region to said oxide on said sidewall of said second polysilicon region.

Claim 11

The contact structure as recited in claim 3 wherein said metal silicide region further extends along and is in contact with a second vertical sidewall.

Claim 12

The contact structure as recited in claim 9 wherein said base is a monocrystalline region.

Claim 13

The contact structure as recited in claim 10 wherein said source or drain is a monocrystalline region.

Claim 14

A contact system for a BiCMOS structure, said BiCMOS structure comprising a polysilicon base contact for a bipolar transistor, a polysilicon emitter contact for said bipolar transistor, said emitter contact having oxide sidewalls thereon, a polysilicon collector contact for said bipolar transistor, polysilicon source and drain contacts for an NMOS transistor, polysilicon source and drain contacts for a PMOS transistor, and polysilicon gates for said NMOS and PMOS transistors, said gates having oxide sidewalls thereon, comprising: a) metal silicide extending along an upper surface of said base contact, down a sidewall of said base contact, and along an upper surface of a monocrystalline bipolar base to said oxide sidewall on said emitter; b) metal silicide extending from said oxide sidewall on said emitter contact to an opposite oxide sidewall on said emitter contact; c) metal silicide along first and second sidewalls of said collector contact and along an upper surface of said collector contact; d) metal silicide along first and second sidewalls of said source and drain contacts and along upper surfaces of said source and drain contacts; e) metal silicide between oxide sidewalls of said gates; and f) metal silicide in contact with monocrystalline source and drain regions of said NMOS and PMOS transistors between said oxide sidewalls of said gates and source and drain contacts.

Claim 16

The method as recited in claim 15 wherein said step of removing also leaves silicide on said substrate between said first sidewall of said second polysilicon region and said oxide remaining on said at least one sidewall.

Claim 17

The method as recited in claim 15 wherein the step of protecting is a step of forming a mask.

Claim 18

The method as recited in claim 15 preceded by the step of forming an oxide region between said first polysilicon region and said substrate, said first polysilicon region, said oxide region between said first polysilicon region and said substrate, and said substrate forming a metal, insulator, semiconductor device.

Claim 19

The method as recited in claim 16 further comprising the step of doping said substrate between said first sidewall of said second polysilicon region and said oxide remaining on said at least one sidewall to a first conductivity type, said substrate below said oxide region between said first polysilicon region and said substrate comprising monocrystalline silicon of a second conductivity type.

Claim 20

The method as recited in claim 16 further comprising the step of providing said substrate below said first polysilicon region with a dopant of a first conductivity type, said first polysilicon region comprising monocrystalline silicon of a second conductivity type.