Patent EP0441684A1 successfully refreshed from Google Patents.
EP0441684A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Phase lock circuit and resulting frequency multiplier
Assignee: Bull SAS
•
Filing: 1991-01-30
•
Granted: —
•
Expires: 2011-01-30
Abstract
Abstract Translated from French Le multiplieur de fréquence 20 est formé d'un circuit verrouillé en phase comprenant un comparateur de phase 11 pour la commande d'une pluralité d'éléments de retard 130-137 fournissant des signaux successivement décalés en phase CL0-CL7 à un additionneur logique 16 fait de portes OU Exclusif. The frequency multiplier 20 is formed by a phase locked circuit comprising a phase comparator 11 for the control of a plurality of delay elements 130-137 supplying successively phase-shifted signals CL0-CL7 to a logic adder 16 made of doors OR Exclusive.
Inventors
- 👤 Roland Marbot
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:45
CPC Classifications
H; H03; H03B; H03B19/00; H03B19/06; H03B19/14; H03K; H03K5/00; H03K5/00006; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/089; H03L7/16
Claims Analysis
Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.
References Cited (Backward Citations)
EP0102598A1
Cited
EP0274606A2
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.